SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1608 | 1608 | 0 | 0 |
OutputsKnown_A | 306057436 | 301081364 | 0 | 0 |
gen_flops.OutputDelay_A | 306057436 | 301066842 | 0 | 4824 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1608 | 1608 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T15 | 2 | 2 | 0 | 0 |
T16 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
T21 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 306057436 | 301081364 | 0 | 0 |
T1 | 757036 | 755950 | 0 | 0 |
T4 | 364354 | 363988 | 0 | 0 |
T5 | 4690 | 4418 | 0 | 0 |
T15 | 62122 | 27530 | 0 | 0 |
T16 | 3616 | 3462 | 0 | 0 |
T17 | 4170 | 4036 | 0 | 0 |
T18 | 2082 | 2052 | 0 | 0 |
T19 | 3904 | 3584 | 0 | 0 |
T20 | 1836 | 1752 | 0 | 0 |
T21 | 2724 | 2314 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 306057436 | 301066842 | 0 | 4824 |
T1 | 757036 | 755896 | 0 | 6 |
T4 | 364354 | 363982 | 0 | 6 |
T5 | 4690 | 4412 | 0 | 6 |
T15 | 62122 | 26900 | 0 | 6 |
T16 | 3616 | 3456 | 0 | 6 |
T17 | 4170 | 4030 | 0 | 6 |
T18 | 2082 | 2046 | 0 | 6 |
T19 | 3904 | 3578 | 0 | 6 |
T20 | 1836 | 1746 | 0 | 6 |
T21 | 2724 | 2308 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 804 | 804 | 0 | 0 |
OutputsKnown_A | 153028718 | 150540682 | 0 | 0 |
gen_flops.OutputDelay_A | 153028718 | 150533421 | 0 | 2412 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 804 | 804 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 153028718 | 150540682 | 0 | 0 |
T1 | 378518 | 377975 | 0 | 0 |
T4 | 182177 | 181994 | 0 | 0 |
T5 | 2345 | 2209 | 0 | 0 |
T15 | 31061 | 13765 | 0 | 0 |
T16 | 1808 | 1731 | 0 | 0 |
T17 | 2085 | 2018 | 0 | 0 |
T18 | 1041 | 1026 | 0 | 0 |
T19 | 1952 | 1792 | 0 | 0 |
T20 | 918 | 876 | 0 | 0 |
T21 | 1362 | 1157 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 153028718 | 150533421 | 0 | 2412 |
T1 | 378518 | 377948 | 0 | 3 |
T4 | 182177 | 181991 | 0 | 3 |
T5 | 2345 | 2206 | 0 | 3 |
T15 | 31061 | 13450 | 0 | 3 |
T16 | 1808 | 1728 | 0 | 3 |
T17 | 2085 | 2015 | 0 | 3 |
T18 | 1041 | 1023 | 0 | 3 |
T19 | 1952 | 1789 | 0 | 3 |
T20 | 918 | 873 | 0 | 3 |
T21 | 1362 | 1154 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 804 | 804 | 0 | 0 |
OutputsKnown_A | 153028718 | 150540682 | 0 | 0 |
gen_flops.OutputDelay_A | 153028718 | 150533421 | 0 | 2412 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 804 | 804 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 153028718 | 150540682 | 0 | 0 |
T1 | 378518 | 377975 | 0 | 0 |
T4 | 182177 | 181994 | 0 | 0 |
T5 | 2345 | 2209 | 0 | 0 |
T15 | 31061 | 13765 | 0 | 0 |
T16 | 1808 | 1731 | 0 | 0 |
T17 | 2085 | 2018 | 0 | 0 |
T18 | 1041 | 1026 | 0 | 0 |
T19 | 1952 | 1792 | 0 | 0 |
T20 | 918 | 876 | 0 | 0 |
T21 | 1362 | 1157 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 153028718 | 150533421 | 0 | 2412 |
T1 | 378518 | 377948 | 0 | 3 |
T4 | 182177 | 181991 | 0 | 3 |
T5 | 2345 | 2206 | 0 | 3 |
T15 | 31061 | 13450 | 0 | 3 |
T16 | 1808 | 1728 | 0 | 3 |
T17 | 2085 | 2015 | 0 | 3 |
T18 | 1041 | 1023 | 0 | 3 |
T19 | 1952 | 1789 | 0 | 3 |
T20 | 918 | 873 | 0 | 3 |
T21 | 1362 | 1154 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |