Module Definition
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Module : prim_lc_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_clkmgr_byp.u_en_sync 100.00 100.00 100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_en_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[1].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_en_sync

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req

Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Module : prim_lc_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 1608 1608 0 0
OutputsKnown_A 306057436 301081364 0 0
gen_flops.OutputDelay_A 306057436 301066842 0 4824


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1608 1608 0 0
T1 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0
T21 2 2 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306057436 301081364 0 0
T1 757036 755950 0 0
T4 364354 363988 0 0
T5 4690 4418 0 0
T15 62122 27530 0 0
T16 3616 3462 0 0
T17 4170 4036 0 0
T18 2082 2052 0 0
T19 3904 3584 0 0
T20 1836 1752 0 0
T21 2724 2314 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 306057436 301066842 0 4824
T1 757036 755896 0 6
T4 364354 363982 0 6
T5 4690 4412 0 6
T15 62122 26900 0 6
T16 3616 3456 0 6
T17 4170 4030 0 6
T18 2082 2046 0 6
T19 3904 3578 0 6
T20 1836 1746 0 6
T21 2724 2308 0 6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 153028718 150540682 0 0
gen_flops.OutputDelay_A 153028718 150533421 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153028718 150540682 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153028718 150533421 0 2412
T1 378518 377948 0 3
T4 182177 181991 0 3
T5 2345 2206 0 3
T15 31061 13450 0 3
T16 1808 1728 0 3
T17 2085 2015 0 3
T18 1041 1023 0 3
T19 1952 1789 0 3
T20 918 873 0 3
T21 1362 1154 0 3

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS6811100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
106 2 2


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 804 804 0 0
OutputsKnown_A 153028718 150540682 0 0
gen_flops.OutputDelay_A 153028718 150533421 0 2412


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 804 804 0 0
T1 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153028718 150540682 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

gen_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153028718 150533421 0 2412
T1 378518 377948 0 3
T4 182177 181991 0 3
T5 2345 2206 0 3
T15 31061 13450 0 3
T16 1808 1728 0 3
T17 2085 2015 0 3
T18 1041 1023 0 3
T19 1952 1789 0 3
T20 918 873 0 3
T21 1362 1154 0 3

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