Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	153028718	19356874	0	61

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	19356874	0	61
T1	378518	70094	0	1
T2	0	52472	0	1
T3	0	243713	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T8	0	2230	0	1
T9	0	30626	0	0
T10	0	86325	0	1
T11	0	3264	0	1
T12	0	46841	0	1
T13	0	23191	0	1
T14	0	3212	0	1
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0
T22	0	0	0	1
T108	0	0	0	1