Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153938329	5233249	0	0
clk_enables_rd_A	153938329	23090	0	0
clk_hints_rd_A	153938329	19475	0	0
extclk_ctrl_rd_A	153938329	27151	0	0
extclk_ctrl_regwen_rd_A	153938329	18724	0	0
jitter_enable_rd_A	153938329	30442	0	0
jitter_regwen_rd_A	153938329	21310	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153938329	5233249	0	0
T3	296074	102242	0	0
T8	15885	0	0	0
T9	206695	103487	0	0
T10	304526	0	0	0
T23	0	39961	0	0
T24	36807	0	0	0
T52	0	182177	0	0
T53	0	130803	0	0
T54	0	135084	0	0
T55	0	50654	0	0
T56	0	62148	0	0
T57	0	154664	0	0
T58	0	140735	0	0
T59	946	0	0	0
T60	1862	0	0	0
T61	1741	0	0	0
T62	2325	0	0	0
T63	1291	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153938329	23090	0	0
T1	378518	3	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0
T23	0	818	0	0
T56	0	1314	0	0
T58	0	5648	0	0
T127	0	8	0	0
T128	0	6	0	0
T129	0	8	0	0
T130	0	8	0	0
T131	0	12	0	0
T132	0	9	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153938329	19475	0	0
T1	378518	8	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0
T23	0	715	0	0
T56	0	1081	0	0
T58	0	4768	0	0
T127	0	3	0	0
T128	0	5	0	0
T129	0	2	0	0
T130	0	6	0	0
T131	0	12	0	0
T133	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153938329	27151	0	0
T1	378518	18	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0
T23	0	872	0	0
T65	0	108	0	0
T134	0	13	0	0
T135	0	10	0	0
T136	0	24	0	0
T137	0	49	0	0
T138	0	32	0	0
T139	0	6	0	0
T140	0	5	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153938329	18724	0	0
T23	138083	683	0	0
T34	1047	0	0	0
T52	369574	0	0	0
T56	0	1156	0	0
T58	0	4780	0	0
T64	223082	0	0	0
T65	0	52	0	0
T93	31348	0	0	0
T138	2095	0	0	0
T139	654	0	0	0
T141	0	47	0	0
T142	0	49	0	0
T143	0	18	0	0
T144	0	1708	0	0
T145	0	44	0	0
T146	0	3289	0	0
T147	1059	0	0	0
T148	1574	0	0	0
T149	82664	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153938329	30442	0	0
T1	378518	176	0	0
T4	182177	0	0	0
T5	2345	0	0	0
T15	31061	0	0	0
T16	1808	0	0	0
T17	2085	0	0	0
T18	1041	0	0	0
T19	1952	0	0	0
T20	918	0	0	0
T21	1362	0	0	0
T23	0	1083	0	0
T56	0	1809	0	0
T58	0	6993	0	0
T127	0	124	0	0
T128	0	110	0	0
T129	0	118	0	0
T130	0	54	0	0
T131	0	214	0	0
T133	0	102	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153938329	21310	0	0
T23	138083	831	0	0
T34	1047	0	0	0
T42	0	225	0	0
T52	369574	0	0	0
T56	0	1249	0	0
T58	0	5817	0	0
T64	223082	0	0	0
T93	31348	0	0	0
T138	2095	0	0	0
T139	654	0	0	0
T144	0	2102	0	0
T146	0	3977	0	0
T147	1059	0	0	0
T148	1574	0	0	0
T149	82664	0	0	0
T150	0	1045	0	0
T151	0	1332	0	0
T152	0	1486	0	0
T153	0	1801	0	0