Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 97.74 86.76 94.92 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 87.44 96.94 84.78 93.02 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.66 96.24 80.88 91.53 90.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 83.59 94.90 76.09 88.37 75.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.39 100.00 93.55 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 97.73 100.00 90.91 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions151386.67
Logical151386.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT3,T9,T25
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T2,T3
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1539383290 1406591 0 0
DstReqKnown_A 2147483647 2147483647 0 0
SrcAckBusyChk_A 1539383290 271578 0 0
SrcBusyKnown_A 1539383290 1513449640 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1539383290 1406591 0 0
T1 3785180 7102 0 0
T2 0 7574 0 0
T3 0 13660 0 0
T4 1821770 2528 0 0
T5 23450 0 0 0
T8 0 905 0 0
T9 0 10806 0 0
T10 0 4277 0 0
T11 0 862 0 0
T15 310610 0 0 0
T16 18080 0 0 0
T17 20850 0 0 0
T18 10410 0 0 0
T19 19520 0 0 0
T20 9180 0 0 0
T21 13620 0 0 0
T24 0 876 0 0
T25 0 246 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 5996988 5989024 0 0
T4 952988 951952 0 0
T5 15596 14808 0 0
T15 185758 87538 0 0
T16 22684 21886 0 0
T17 13410 13030 0 0
T18 28548 28168 0 0
T19 13182 12234 0 0
T20 32076 30758 0 0
T21 8826 7586 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1539383290 271578 0 0
T1 3785180 1600 0 0
T2 0 2240 0 0
T3 0 1640 0 0
T4 1821770 300 0 0
T5 23450 0 0 0
T8 0 360 0 0
T9 0 3795 0 0
T10 0 520 0 0
T11 0 320 0 0
T15 310610 0 0 0
T16 18080 0 0 0
T17 20850 0 0 0
T18 10410 0 0 0
T19 19520 0 0 0
T20 9180 0 0 0
T21 13620 0 0 0
T24 0 260 0 0
T25 0 29 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1539383290 1513449640 0 0
T1 3785180 3779750 0 0
T4 1821770 1819940 0 0
T5 23450 22090 0 0
T15 310610 137650 0 0
T16 18080 17310 0 0
T17 20850 20180 0 0
T18 10410 10260 0 0
T19 19520 17920 0 0
T20 9180 8760 0 0
T21 13620 11570 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T2,T3
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 88235 0 0
DstReqKnown_A 467156873 462554265 0 0
SrcAckBusyChk_A 153938329 24303 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 88235 0 0
T1 378518 526 0 0
T2 0 558 0 0
T3 0 810 0 0
T4 182177 154 0 0
T5 2345 0 0 0
T8 0 90 0 0
T9 0 939 0 0
T10 0 263 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 66 0 0
T25 0 12 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467156873 462554265 0 0
T1 881357 879974 0 0
T4 140326 140150 0 0
T5 2320 2185 0 0
T15 30118 13295 0 0
T16 3473 3324 0 0
T17 2042 1975 0 0
T18 4345 4278 0 0
T19 1973 1811 0 0
T20 4903 4672 0 0
T21 1348 1145 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 24303 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 158 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 377 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T2,T3
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 122810 0 0
DstReqKnown_A 232721492 231565765 0 0
SrcAckBusyChk_A 153938329 24303 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 122810 0 0
T1 378518 711 0 0
T2 0 784 0 0
T3 0 1299 0 0
T4 182177 242 0 0
T5 2345 0 0 0
T8 0 90 0 0
T9 0 1023 0 0
T10 0 424 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 89 0 0
T25 0 19 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 232721492 231565765 0 0
T1 440432 440120 0 0
T4 70123 70075 0 0
T5 1269 1234 0 0
T15 10887 6648 0 0
T16 1676 1662 0 0
T17 1010 996 0 0
T18 2153 2139 0 0
T19 1052 1011 0 0
T20 2384 2336 0 0
T21 659 590 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 24303 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 158 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 377 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T2,T3
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 195935 0 0
DstReqKnown_A 116360140 115782368 0 0
SrcAckBusyChk_A 153938329 24303 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 195935 0 0
T1 378518 1094 0 0
T2 0 1113 0 0
T3 0 2280 0 0
T4 182177 438 0 0
T5 2345 0 0 0
T8 0 93 0 0
T9 0 1423 0 0
T10 0 730 0 0
T11 0 106 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 125 0 0
T25 0 31 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116360140 115782368 0 0
T1 220215 220060 0 0
T4 35062 35038 0 0
T5 632 615 0 0
T15 5439 3323 0 0
T16 838 831 0 0
T17 504 497 0 0
T18 1077 1070 0 0
T19 525 504 0 0
T20 1192 1168 0 0
T21 329 295 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 24303 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 158 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 377 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T2,T3
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 84920 0 0
DstReqKnown_A 497151489 492313777 0 0
SrcAckBusyChk_A 153938329 24303 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 84920 0 0
T1 378518 520 0 0
T2 0 544 0 0
T3 0 939 0 0
T4 182177 180 0 0
T5 2345 0 0 0
T8 0 90 0 0
T9 0 939 0 0
T10 0 307 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 66 0 0
T25 0 12 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 497151489 492313777 0 0
T1 984110 982667 0 0
T4 152177 151994 0 0
T5 2417 2277 0 0
T15 31375 13851 0 0
T16 3618 3463 0 0
T17 2128 2059 0 0
T18 4526 4457 0 0
T19 2055 1886 0 0
T20 5108 4867 0 0
T21 1403 1191 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 24303 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 158 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 377 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 2 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT1,T2,T3
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 120335 0 0
DstReqKnown_A 238522863 236199621 0 0
SrcAckBusyChk_A 153938329 23821 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 120335 0 0
T1 378518 706 0 0
T2 0 784 0 0
T3 0 1298 0 0
T4 182177 252 0 0
T5 2345 0 0 0
T8 0 90 0 0
T9 0 1029 0 0
T10 0 426 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 92 0 0
T25 0 10 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238522863 236199621 0 0
T1 472380 471691 0 0
T4 78806 78719 0 0
T5 1160 1093 0 0
T15 15060 6652 0 0
T16 1737 1663 0 0
T17 1021 988 0 0
T18 2173 2140 0 0
T19 986 905 0 0
T20 2451 2336 0 0
T21 674 572 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 23821 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 158 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 377 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 1 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT3,T9,T25
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 112257 0 0
DstReqKnown_A 467156873 462554265 0 0
SrcAckBusyChk_A 153938329 30123 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 112257 0 0
T1 378518 529 0 0
T2 0 562 0 0
T3 0 868 0 0
T4 182177 153 0 0
T5 2345 0 0 0
T8 0 89 0 0
T9 0 950 0 0
T10 0 262 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 66 0 0
T25 0 20 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 467156873 462554265 0 0
T1 881357 879974 0 0
T4 140326 140150 0 0
T5 2320 2185 0 0
T15 30118 13295 0 0
T16 3473 3324 0 0
T17 2042 1975 0 0
T18 4345 4278 0 0
T19 1973 1811 0 0
T20 4903 4672 0 0
T21 1348 1145 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 30123 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 170 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 382 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 4 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT3,T9,T25
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 159301 0 0
DstReqKnown_A 232721492 231565765 0 0
SrcAckBusyChk_A 153938329 30257 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 159301 0 0
T1 378518 707 0 0
T2 0 785 0 0
T3 0 1375 0 0
T4 182177 247 0 0
T5 2345 0 0 0
T8 0 89 0 0
T9 0 1057 0 0
T10 0 422 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 91 0 0
T25 0 33 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 232721492 231565765 0 0
T1 440432 440120 0 0
T4 70123 70075 0 0
T5 1269 1234 0 0
T15 10887 6648 0 0
T16 1676 1662 0 0
T17 1010 996 0 0
T18 2153 2139 0 0
T19 1052 1011 0 0
T20 2384 2336 0 0
T21 659 590 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 30257 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 170 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 382 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 4 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT3,T9,T25
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 256897 0 0
DstReqKnown_A 116360140 115782368 0 0
SrcAckBusyChk_A 153938329 30180 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 256897 0 0
T1 378518 1091 0 0
T2 0 1118 0 0
T3 0 2402 0 0
T4 182177 437 0 0
T5 2345 0 0 0
T8 0 96 0 0
T9 0 1443 0 0
T10 0 718 0 0
T11 0 108 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 124 0 0
T25 0 57 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 116360140 115782368 0 0
T1 220215 220060 0 0
T4 35062 35038 0 0
T5 632 615 0 0
T15 5439 3323 0 0
T16 838 831 0 0
T17 504 497 0 0
T18 1077 1070 0 0
T19 525 504 0 0
T20 1192 1168 0 0
T21 329 295 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 30180 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 170 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 382 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 4 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT3,T9,T25
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 108543 0 0
DstReqKnown_A 497151489 492313777 0 0
SrcAckBusyChk_A 153938329 30137 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 108543 0 0
T1 378518 513 0 0
T2 0 543 0 0
T3 0 1012 0 0
T4 182177 180 0 0
T5 2345 0 0 0
T8 0 89 0 0
T9 0 950 0 0
T10 0 306 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 66 0 0
T25 0 20 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 497151489 492313777 0 0
T1 984110 982667 0 0
T4 152177 151994 0 0
T5 2417 2277 0 0
T15 31375 13851 0 0
T16 3618 3463 0 0
T17 2128 2059 0 0
T18 4526 4457 0 0
T19 2055 1886 0 0
T20 5108 4867 0 0
T21 1403 1191 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 30137 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 170 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 382 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 4 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalCoveredPercent
Conditions121191.67
Logical121191.67
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T5,T4
01CoveredT3,T9,T25
10CoveredT1,T4,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T5,T4
01Unreachable
10CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T2
11CoveredT1,T4,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T5,T4
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T5,T4
0 1 - Covered T1,T4,T2
0 0 1 Covered T1,T4,T2
0 0 0 Covered T1,T5,T4


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 153938329 157358 0 0
DstReqKnown_A 238522863 236199621 0 0
SrcAckBusyChk_A 153938329 29848 0 0
SrcBusyKnown_A 153938329 151344964 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 157358 0 0
T1 378518 705 0 0
T2 0 783 0 0
T3 0 1377 0 0
T4 182177 245 0 0
T5 2345 0 0 0
T8 0 89 0 0
T9 0 1053 0 0
T10 0 419 0 0
T11 0 81 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 91 0 0
T25 0 32 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 238522863 236199621 0 0
T1 472380 471691 0 0
T4 78806 78719 0 0
T5 1160 1093 0 0
T15 15060 6652 0 0
T16 1737 1663 0 0
T17 1021 988 0 0
T18 2173 2140 0 0
T19 986 905 0 0
T20 2451 2336 0 0
T21 674 572 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 29848 0 0
T1 378518 160 0 0
T2 0 224 0 0
T3 0 170 0 0
T4 182177 30 0 0
T5 2345 0 0 0
T8 0 36 0 0
T9 0 382 0 0
T10 0 52 0 0
T11 0 32 0 0
T15 31061 0 0 0
T16 1808 0 0 0
T17 2085 0 0 0
T18 1041 0 0 0
T19 1952 0 0 0
T20 918 0 0 0
T21 1362 0 0 0
T24 0 26 0 0
T25 0 4 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 153938329 151344964 0 0
T1 378518 377975 0 0
T4 182177 181994 0 0
T5 2345 2209 0 0
T15 31061 13765 0 0
T16 1808 1731 0 0
T17 2085 2018 0 0
T18 1041 1026 0 0
T19 1952 1792 0 0
T20 918 876 0 0
T21 1362 1157 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%