Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T5,T17
11CoveredT1,T5,T17

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 465028432 4431 0 0
g_div2.Div2Whole_A 465028432 5245 0 0
g_div4.Div4Stepped_A 231704779 4328 0 0
g_div4.Div4Whole_A 231704779 4961 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 465028432 4431 0 0
T1 881358 3 0 0
T2 0 1 0 0
T3 0 43 0 0
T4 140326 0 0 0
T5 2320 9 0 0
T15 30119 0 0 0
T16 3474 0 0 0
T17 2043 0 0 0
T18 4346 0 0 0
T19 1973 4 0 0
T20 4903 0 0 0
T21 1348 1 0 0
T38 0 5 0 0
T59 0 1 0 0
T103 0 2 0 0
T104 0 7 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 465028432 5245 0 0
T1 881358 4 0 0
T2 0 2 0 0
T3 0 54 0 0
T4 140326 0 0 0
T5 2320 11 0 0
T15 30119 0 0 0
T16 3474 0 0 0
T17 2043 3 0 0
T18 4346 0 0 0
T19 1973 9 0 0
T20 4903 0 0 0
T21 1348 1 0 0
T38 0 8 0 0
T103 0 2 0 0
T104 0 7 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231704779 4328 0 0
T1 440432 3 0 0
T2 0 1 0 0
T3 0 41 0 0
T4 70124 0 0 0
T5 1270 9 0 0
T15 10887 0 0 0
T16 1677 0 0 0
T17 1010 0 0 0
T18 2154 0 0 0
T19 1052 4 0 0
T20 2385 0 0 0
T21 660 1 0 0
T38 0 4 0 0
T59 0 1 0 0
T103 0 2 0 0
T104 0 7 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231704779 4961 0 0
T1 440432 4 0 0
T2 0 2 0 0
T3 0 46 0 0
T4 70124 0 0 0
T5 1270 8 0 0
T15 10887 0 0 0
T16 1677 0 0 0
T17 1010 3 0 0
T18 2154 0 0 0
T19 1052 6 0 0
T20 2385 0 0 0
T21 660 1 0 0
T38 0 8 0 0
T103 0 2 0 0
T104 0 7 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T5,T17
11CoveredT1,T5,T17

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 465028432 4431 0 0
g_div2.Div2Whole_A 465028432 5245 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 465028432 4431 0 0
T1 881358 3 0 0
T2 0 1 0 0
T3 0 43 0 0
T4 140326 0 0 0
T5 2320 9 0 0
T15 30119 0 0 0
T16 3474 0 0 0
T17 2043 0 0 0
T18 4346 0 0 0
T19 1973 4 0 0
T20 4903 0 0 0
T21 1348 1 0 0
T38 0 5 0 0
T59 0 1 0 0
T103 0 2 0 0
T104 0 7 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 465028432 5245 0 0
T1 881358 4 0 0
T2 0 2 0 0
T3 0 54 0 0
T4 140326 0 0 0
T5 2320 11 0 0
T15 30119 0 0 0
T16 3474 0 0 0
T17 2043 3 0 0
T18 4346 0 0 0
T19 1973 9 0 0
T20 4903 0 0 0
T21 1348 1 0 0
T38 0 8 0 0
T103 0 2 0 0
T104 0 7 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T5,T4
10CoveredT1,T5,T17
11CoveredT1,T5,T17

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 231704779 4328 0 0
g_div4.Div4Whole_A 231704779 4961 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231704779 4328 0 0
T1 440432 3 0 0
T2 0 1 0 0
T3 0 41 0 0
T4 70124 0 0 0
T5 1270 9 0 0
T15 10887 0 0 0
T16 1677 0 0 0
T17 1010 0 0 0
T18 2154 0 0 0
T19 1052 4 0 0
T20 2385 0 0 0
T21 660 1 0 0
T38 0 4 0 0
T59 0 1 0 0
T103 0 2 0 0
T104 0 7 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 231704779 4961 0 0
T1 440432 4 0 0
T2 0 2 0 0
T3 0 46 0 0
T4 70124 0 0 0
T5 1270 8 0 0
T15 10887 0 0 0
T16 1677 0 0 0
T17 1010 3 0 0
T18 2154 0 0 0
T19 1052 6 0 0
T20 2385 0 0 0
T21 660 1 0 0
T38 0 8 0 0
T103 0 2 0 0
T104 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%