Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	459086154	430	0	0
StatusRise_A	459086154	430	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459086154	430	0	0
T2	1041072	0	0	0
T3	888222	0	0	0
T31	8904	0	0	0
T32	4245	9	0	0
T33	0	4	0	0
T34	0	15	0	0
T35	0	1	0	0
T38	7173	0	0	0
T51	10407	0	0	0
T59	2838	0	0	0
T60	5586	0	0	0
T103	5187	0	0	0
T104	5445	0	0	0
T154	0	8	0	0
T155	0	4	0	0
T156	0	13	0	0
T157	0	9	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	16	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459086154	430	0	0
T2	1041072	0	0	0
T3	888222	0	0	0
T31	8904	0	0	0
T32	4245	9	0	0
T33	0	4	0	0
T34	0	15	0	0
T35	0	1	0	0
T38	7173	0	0	0
T51	10407	0	0	0
T59	2838	0	0	0
T60	5586	0	0	0
T103	5187	0	0	0
T104	5445	0	0	0
T154	0	8	0	0
T155	0	4	0	0
T156	0	13	0	0
T157	0	9	0	0
T158	0	6	0	0
T159	0	2	0	0
T160	0	16	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	153028718	142	0	0
StatusRise_A	153028718	142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	142	0	0
T2	347024	0	0	0
T3	296074	0	0	0
T31	2968	0	0	0
T32	1415	2	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2391	0	0	0
T51	3469	0	0	0
T59	946	0	0	0
T60	1862	0	0	0
T103	1729	0	0	0
T104	1815	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	142	0	0
T2	347024	0	0	0
T3	296074	0	0	0
T31	2968	0	0	0
T32	1415	2	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2391	0	0	0
T51	3469	0	0	0
T59	946	0	0	0
T60	1862	0	0	0
T103	1729	0	0	0
T104	1815	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	153028718	136	0	0
StatusRise_A	153028718	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	136	0	0
T2	347024	0	0	0
T3	296074	0	0	0
T31	2968	0	0	0
T32	1415	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2391	0	0	0
T51	3469	0	0	0
T59	946	0	0	0
T60	1862	0	0	0
T103	1729	0	0	0
T104	1815	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	136	0	0
T2	347024	0	0	0
T3	296074	0	0	0
T31	2968	0	0	0
T32	1415	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2391	0	0	0
T51	3469	0	0	0
T59	946	0	0	0
T60	1862	0	0	0
T103	1729	0	0	0
T104	1815	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	153028718	152	0	0
StatusRise_A	153028718	152	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	152	0	0
T2	347024	0	0	0
T3	296074	0	0	0
T31	2968	0	0	0
T32	1415	4	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	1	0	0
T38	2391	0	0	0
T51	3469	0	0	0
T59	946	0	0	0
T60	1862	0	0	0
T103	1729	0	0	0
T104	1815	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	4	0	0
T158	0	2	0	0
T160	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153028718	152	0	0
T2	347024	0	0	0
T3	296074	0	0	0
T31	2968	0	0	0
T32	1415	4	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	1	0	0
T38	2391	0	0	0
T51	3469	0	0	0
T59	946	0	0	0
T60	1862	0	0	0
T103	1729	0	0	0
T104	1815	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	4	0	0
T158	0	2	0	0
T160	0	6	0	0