Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	49066	0	0
CgEnOn_A	2147483647	39601	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	49066	0	0
T1	5950824	64	0	0
T2	2558867	0	0	0
T3	3231304	0	0	0
T4	933025	3	0	0
T5	15049	3	0	0
T15	187004	303	0	0
T16	22196	3	0	0
T17	13089	3	0	0
T18	27852	7	0	0
T19	12756	3	0	0
T20	31362	3	0	0
T21	8622	3	0	0
T31	50960	8	0	0
T32	6549	17	0	0
T33	0	5	0	0
T34	0	25	0	0
T38	11787	0	0	0
T51	16874	0	0	0
T52	0	5	0	0
T56	0	5	0	0
T57	0	5	0	0
T59	18367	0	0	0
T60	9068	0	0	0
T103	8368	0	0	0
T104	41348	0	0	0
T154	0	10	0	0
T155	0	10	0	0
T156	0	15	0	0
T157	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39601	0	0
T1	5950824	13	0	0
T2	2558867	53	0	0
T3	3231304	99	0	0
T4	933025	0	0	0
T5	15049	0	0	0
T9	0	93	0	0
T15	187004	0	0	0
T16	22196	0	0	0
T17	13089	0	0	0
T18	27852	2	0	0
T19	12756	0	0	0
T20	31362	0	0	0
T21	8622	0	0	0
T31	50960	0	0	0
T32	6549	21	0	0
T33	0	5	0	0
T34	0	25	0	0
T38	11787	0	0	0
T51	16874	0	0	0
T52	0	5	0	0
T56	0	5	0	0
T57	0	4	0	0
T59	18367	0	0	0
T60	9068	0	0	0
T61	0	1	0	0
T63	0	9	0	0
T103	8368	0	0	0
T104	41348	0	0	0
T154	0	10	0	0
T155	0	10	0	0
T156	0	15	0	0
T157	0	10	0	0
T158	0	2	0	0
T161	0	14	0	0
T162	0	13	0	0
T163	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	231704379	142	0	0
CgEnOn_A	231704379	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231704379	142	0	0
T2	605388	0	0	0
T3	139039	0	0	0
T31	5258	0	0	0
T32	658	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	1255	0	0	0
T51	1726	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	1919	0	0	0
T60	989	0	0	0
T103	870	0	0	0
T104	4648	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231704379	142	0	0
T2	605388	0	0	0
T3	139039	0	0	0
T31	5258	0	0	0
T32	658	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	1255	0	0	0
T51	1726	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	1919	0	0	0
T60	989	0	0	0
T103	870	0	0	0
T104	4648	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115851573	142	0	0
CgEnOn_A	115851573	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	142	0	0
T2	302694	0	0	0
T3	695192	0	0	0
T31	2629	0	0	0
T32	329	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	626	0	0	0
T51	863	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	960	0	0	0
T60	493	0	0	0
T103	434	0	0	0
T104	2324	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	142	0	0
T2	302694	0	0	0
T3	695192	0	0	0
T31	2629	0	0	0
T32	329	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	626	0	0	0
T51	863	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	960	0	0	0
T60	493	0	0	0
T103	434	0	0	0
T104	2324	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115851573	142	0	0
CgEnOn_A	115851573	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	142	0	0
T2	302694	0	0	0
T3	695192	0	0	0
T31	2629	0	0	0
T32	329	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	626	0	0	0
T51	863	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	960	0	0	0
T60	493	0	0	0
T103	434	0	0	0
T104	2324	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	142	0	0
T2	302694	0	0	0
T3	695192	0	0	0
T31	2629	0	0	0
T32	329	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	626	0	0	0
T51	863	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	960	0	0	0
T60	493	0	0	0
T103	434	0	0	0
T104	2324	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115851573	142	0	0
CgEnOn_A	115851573	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	142	0	0
T2	302694	0	0	0
T3	695192	0	0	0
T31	2629	0	0	0
T32	329	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	626	0	0	0
T51	863	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	960	0	0	0
T60	493	0	0	0
T103	434	0	0	0
T104	2324	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	142	0	0
T2	302694	0	0	0
T3	695192	0	0	0
T31	2629	0	0	0
T32	329	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	626	0	0	0
T51	863	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	960	0	0	0
T60	493	0	0	0
T103	434	0	0	0
T104	2324	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	465028000	142	0	0
CgEnOn_A	465028000	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465028000	142	0	0
T2	121158	0	0	0
T3	279039	0	0	0
T31	10553	0	0	0
T32	1368	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2415	0	0	0
T51	3505	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	3787	0	0	0
T60	1842	0	0	0
T103	1729	0	0	0
T104	8296	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465028000	139	0	0
T2	121158	0	0	0
T3	279039	0	0	0
T31	10553	0	0	0
T32	1368	3	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2415	0	0	0
T51	3505	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T59	3787	0	0	0
T60	1842	0	0	0
T103	1729	0	0	0
T104	8296	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494933814	144	0	0
CgEnOn_A	494933814	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	144	0	0
T2	137610	0	0	0
T3	293198	1	0	0
T31	10993	0	0	0
T32	1435	2	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2516	0	0	0
T51	3651	0	0	0
T59	3944	0	0	0
T60	1919	0	0	0
T103	1801	0	0	0
T104	8642	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	143	0	0
T2	137610	0	0	0
T3	293198	1	0	0
T31	10993	0	0	0
T32	1435	2	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2516	0	0	0
T51	3651	0	0	0
T59	3944	0	0	0
T60	1919	0	0	0
T103	1801	0	0	0
T104	8642	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494933814	144	0	0
CgEnOn_A	494933814	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	144	0	0
T2	137610	0	0	0
T3	293198	1	0	0
T31	10993	0	0	0
T32	1435	2	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2516	0	0	0
T51	3651	0	0	0
T59	3944	0	0	0
T60	1919	0	0	0
T103	1801	0	0	0
T104	8642	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	143	0	0
T2	137610	0	0	0
T3	293198	1	0	0
T31	10993	0	0	0
T32	1435	2	0	0
T33	0	1	0	0
T34	0	5	0	0
T38	2516	0	0	0
T51	3651	0	0	0
T59	3944	0	0	0
T60	1919	0	0	0
T103	1801	0	0	0
T104	8642	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	3	0	0
T158	0	2	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Unreachable
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	237458420	153	0	0
CgEnOn_A	237458420	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237458420	153	0	0
T2	649019	0	0	0
T3	141254	0	0	0
T31	5276	0	0	0
T32	666	4	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	1	0	0
T38	1207	0	0	0
T51	1752	0	0	0
T59	1893	0	0	0
T60	920	0	0	0
T103	865	0	0	0
T104	4148	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	4	0	0
T158	0	2	0	0
T160	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237458420	153	0	0
T2	649019	0	0	0
T3	141254	0	0	0
T31	5276	0	0	0
T32	666	4	0	0
T33	0	2	0	0
T34	0	5	0	0
T35	0	1	0	0
T38	1207	0	0	0
T51	1752	0	0	0
T59	1893	0	0	0
T60	920	0	0	0
T103	865	0	0	0
T104	4148	0	0	0
T154	0	3	0	0
T155	0	1	0	0
T156	0	5	0	0
T157	0	4	0	0
T158	0	2	0	0
T160	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115851573	7666	0	0
CgEnOn_A	115851573	5304	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	7666	0	0
T1	220215	15	0	0
T4	35062	1	0	0
T5	632	1	0	0
T15	5439	101	0	0
T16	838	1	0	0
T17	504	1	0	0
T18	1077	2	0	0
T19	525	1	0	0
T20	1192	1	0	0
T21	329	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115851573	5304	0	0
T1	220215	6	0	0
T2	0	27	0	0
T3	0	47	0	0
T4	35062	0	0	0
T5	632	0	0	0
T9	0	45	0	0
T15	5439	0	0	0
T16	838	0	0	0
T17	504	0	0	0
T18	1077	1	0	0
T19	525	0	0	0
T20	1192	0	0	0
T21	329	0	0	0
T32	0	3	0	0
T63	0	5	0	0
T161	0	7	0	0
T162	0	6	0	0
T163	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	231704379	7712	0	0
CgEnOn_A	231704379	5350	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231704379	7712	0	0
T1	440432	16	0	0
T4	70123	1	0	0
T5	1269	1	0	0
T15	10887	101	0	0
T16	1676	1	0	0
T17	1010	1	0	0
T18	2153	2	0	0
T19	1052	1	0	0
T20	2384	1	0	0
T21	659	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231704379	5350	0	0
T1	440432	7	0	0
T2	0	26	0	0
T3	0	52	0	0
T4	70123	0	0	0
T5	1269	0	0	0
T9	0	48	0	0
T15	10887	0	0	0
T16	1676	0	0	0
T17	1010	0	0	0
T18	2153	1	0	0
T19	1052	0	0	0
T20	2384	0	0	0
T21	659	0	0	0
T32	0	3	0	0
T61	0	1	0	0
T63	0	4	0	0
T161	0	7	0	0
T162	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	465028000	7717	0	0
CgEnOn_A	465028000	5352	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465028000	7717	0	0
T1	881357	15	0	0
T4	140326	1	0	0
T5	2320	1	0	0
T15	30118	101	0	0
T16	3473	1	0	0
T17	2042	1	0	0
T18	4345	2	0	0
T19	1973	1	0	0
T20	4903	1	0	0
T21	1348	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	465028000	5352	0	0
T1	881357	6	0	0
T2	0	28	0	0
T3	0	50	0	0
T4	140326	0	0	0
T5	2320	0	0	0
T9	0	45	0	0
T15	30118	0	0	0
T16	3473	0	0	0
T17	2042	0	0	0
T18	4345	1	0	0
T19	1973	0	0	0
T20	4903	0	0	0
T21	1348	0	0	0
T32	0	3	0	0
T61	0	1	0	0
T63	0	5	0	0
T161	0	8	0	0
T162	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T32,T35,T33
1	0	Covered	T1,T5,T4
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	237458420	7746	0	0
CgEnOn_A	237458420	5379	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237458420	7746	0	0
T1	472380	16	0	0
T4	78806	1	0	0
T5	1160	1	0	0
T15	15060	101	0	0
T16	1737	1	0	0
T17	1021	1	0	0
T18	2173	2	0	0
T19	986	1	0	0
T20	2451	1	0	0
T21	674	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237458420	5379	0	0
T1	472380	7	0	0
T2	0	26	0	0
T3	0	45	0	0
T4	78806	0	0	0
T5	1160	0	0	0
T9	0	43	0	0
T15	15060	0	0	0
T16	1737	0	0	0
T17	1021	0	0	0
T18	2173	1	0	0
T19	986	0	0	0
T20	2451	0	0	0
T21	674	0	0	0
T32	0	4	0	0
T61	0	1	0	0
T63	0	5	0	0
T161	0	9	0	0
T162	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Covered	T1,T18,T31
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494933814	4215	0	0
CgEnOn_A	494933814	4214	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4215	0	0
T1	984110	18	0	0
T2	0	19	0	0
T3	0	53	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	61	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	0	0	0
T21	1403	0	0	0
T31	0	8	0	0
T32	0	2	0	0
T51	0	11	0	0
T61	0	1	0	0
T105	0	12	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4214	0	0
T1	984110	18	0	0
T2	0	19	0	0
T3	0	53	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	61	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	0	0	0
T21	1403	0	0	0
T31	0	8	0	0
T32	0	2	0	0
T51	0	11	0	0
T61	0	1	0	0
T105	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Covered	T1,T18,T20
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494933814	4230	0	0
CgEnOn_A	494933814	4229	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4230	0	0
T1	984110	23	0	0
T2	0	23	0	0
T3	0	56	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	51	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	1	0	0
T21	1403	0	0	0
T31	0	9	0	0
T32	0	2	0	0
T51	0	8	0	0
T61	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4229	0	0
T1	984110	23	0	0
T2	0	23	0	0
T3	0	56	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	51	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	1	0	0
T21	1403	0	0	0
T31	0	9	0	0
T32	0	2	0	0
T51	0	8	0	0
T61	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Covered	T1,T18,T20
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494933814	4333	0	0
CgEnOn_A	494933814	4332	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4333	0	0
T1	984110	24	0	0
T2	0	16	0	0
T3	0	59	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	54	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	1	0	0
T21	1403	0	0	0
T31	0	9	0	0
T32	0	2	0	0
T51	0	7	0	0
T61	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4332	0	0
T1	984110	24	0	0
T2	0	16	0	0
T3	0	59	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	54	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	1	0	0
T21	1403	0	0	0
T31	0	9	0	0
T32	0	2	0	0
T51	0	7	0	0
T61	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T32
1	0	Covered	T1,T18,T20
1	1	Covered	T1,T5,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	494933814	4296	0	0
CgEnOn_A	494933814	4295	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4296	0	0
T1	984110	30	0	0
T2	0	29	0	0
T3	0	52	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	59	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	2	0	0
T21	1403	0	0	0
T31	0	7	0	0
T32	0	2	0	0
T51	0	9	0	0
T61	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	494933814	4295	0	0
T1	984110	30	0	0
T2	0	29	0	0
T3	0	52	0	0
T4	152177	0	0	0
T5	2417	0	0	0
T9	0	59	0	0
T15	31375	0	0	0
T16	3618	0	0	0
T17	2128	0	0	0
T18	4526	1	0	0
T19	2055	0	0	0
T20	5108	2	0	0
T21	1403	0	0	0
T31	0	7	0	0
T32	0	2	0	0
T51	0	9	0	0
T61	0	1	0	0