Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	625149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3546056

1

T6

15

T4

132

T7

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1023670	1			T6	18		T4	11		T7	24
values[0x0]	1446487	1			T6	19		T4	117		T7	11
values[0x1]	1701048	1			T6	18		T4	115		T7	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3824760

1

T6

21

T4

163

T7

18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15826	1			T16	2		T19	1		T2	673
valid_sources[0x01]	17375	1			T4	16		T16	1		T2	770
valid_sources[0x02]	16543	1			T22	1		T2	783		T3	2
valid_sources[0x03]	15139	1			T16	1		T18	1		T2	619
valid_sources[0x04]	16651	1			T16	3		T19	1		T2	634
valid_sources[0x05]	17107	1			T7	4		T19	1		T2	621
valid_sources[0x06]	16175	1			T22	1		T16	1		T19	1
valid_sources[0x07]	16229	1			T16	1		T2	639		T25	3
valid_sources[0x08]	17246	1			T15	1		T16	2		T2	560
valid_sources[0x09]	15750	1			T4	5		T16	2		T2	671
valid_sources[0x0a]	15651	1			T16	2		T2	745		T3	4
valid_sources[0x0b]	15927	1			T16	2		T2	648		T3	3
valid_sources[0x0c]	15464	1			T16	2		T2	667		T3	5
valid_sources[0x0d]	16460	1			T15	1		T2	672		T8	3
valid_sources[0x0e]	16908	1			T16	1		T2	700		T3	2
valid_sources[0x0f]	17112	1			T16	4		T19	1		T2	663
valid_sources[0x10]	17427	1			T16	3		T18	1		T2	631
valid_sources[0x11]	18038	1			T7	3		T16	2		T2	768
valid_sources[0x12]	19242	1			T2	590		T3	6		T8	2
valid_sources[0x13]	15958	1			T22	2		T2	753		T21	4
valid_sources[0x14]	16402	1			T4	5		T18	1		T2	553
valid_sources[0x15]	16785	1			T16	3		T2	866		T3	5
valid_sources[0x16]	15975	1			T16	5		T2	709		T3	5
valid_sources[0x17]	14680	1			T4	2		T2	681		T25	1
valid_sources[0x18]	16368	1			T16	5		T2	656		T21	7
valid_sources[0x19]	16055	1			T16	2		T18	2		T2	669
valid_sources[0x1a]	16104	1			T4	5		T22	4		T2	687
valid_sources[0x1b]	16761	1			T2	622		T3	2		T8	4
valid_sources[0x1c]	16673	1			T16	1		T19	1		T2	686
valid_sources[0x1d]	16352	1			T16	3		T2	618		T3	2
valid_sources[0x1e]	16277	1			T16	1		T19	1		T2	603
valid_sources[0x1f]	15863	1			T2	662		T3	4		T105	1
valid_sources[0x20]	16503	1			T2	597		T3	3		T29	1
valid_sources[0x21]	15861	1			T18	1		T2	634		T3	5
valid_sources[0x22]	15995	1			T22	1		T16	1		T2	690
valid_sources[0x23]	17300	1			T4	2		T16	3		T2	596
valid_sources[0x24]	16499	1			T22	2		T2	630		T3	3
valid_sources[0x25]	17308	1			T16	1		T19	1		T2	651
valid_sources[0x26]	16000	1			T7	4		T16	4		T2	771
valid_sources[0x27]	15476	1			T16	1		T19	1		T2	591
valid_sources[0x28]	16203	1			T16	2		T2	654		T3	2
valid_sources[0x29]	15532	1			T4	5		T19	1		T2	667
valid_sources[0x2a]	15601	1			T19	1		T2	611		T3	4
valid_sources[0x2b]	18614	1			T2	591		T3	5		T80	3
valid_sources[0x2c]	17079	1			T4	5		T16	2		T2	745
valid_sources[0x2d]	15234	1			T4	1		T15	1		T16	1
valid_sources[0x2e]	15911	1			T16	2		T2	701		T3	2
valid_sources[0x2f]	15705	1			T2	609		T26	112		T3	3
valid_sources[0x30]	16267	1			T2	611		T3	3		T8	2
valid_sources[0x31]	15469	1			T2	560		T3	5		T8	2
valid_sources[0x32]	16632	1			T22	3		T2	650		T3	3
valid_sources[0x33]	15765	1			T2	615		T3	6		T27	1
valid_sources[0x34]	17269	1			T22	1		T16	1		T2	609
valid_sources[0x35]	16530	1			T16	3		T2	624		T3	4
valid_sources[0x36]	15348	1			T4	14		T15	1		T16	1
valid_sources[0x37]	16448	1			T22	2		T16	1		T2	809
valid_sources[0x38]	17056	1			T19	1		T2	595		T3	1
valid_sources[0x39]	16848	1			T16	4		T2	762		T3	3
valid_sources[0x3a]	15813	1			T16	2		T2	693		T25	2
valid_sources[0x3b]	15797	1			T22	1		T2	671		T3	4
valid_sources[0x3c]	16364	1			T16	3		T2	646		T3	2
valid_sources[0x3d]	16010	1			T2	715		T3	6		T8	1
valid_sources[0x3e]	15347	1			T16	5		T2	650		T3	4
valid_sources[0x3f]	16569	1			T22	2		T16	2		T2	740
valid_sources[0x40]	18463	1			T19	1		T2	670		T3	4
valid_sources[0x41]	15719	1			T16	4		T19	1		T2	711
valid_sources[0x42]	17957	1			T2	560		T3	1		T8	1
valid_sources[0x43]	15876	1			T4	8		T16	5		T2	717
valid_sources[0x44]	16558	1			T16	3		T2	583		T3	7
valid_sources[0x45]	16024	1			T2	639		T3	5		T105	1
valid_sources[0x46]	17376	1			T16	1		T19	1		T2	716
valid_sources[0x47]	15187	1			T16	1		T2	556		T3	8
valid_sources[0x48]	16634	1			T7	2		T16	3		T2	645
valid_sources[0x49]	15551	1			T22	1		T16	4		T2	603
valid_sources[0x4a]	14784	1			T2	554		T3	3		T8	2
valid_sources[0x4b]	15369	1			T6	2		T22	1		T16	8
valid_sources[0x4c]	16689	1			T16	1		T2	658		T3	4
valid_sources[0x4d]	17174	1			T22	1		T16	1		T2	687
valid_sources[0x4e]	15393	1			T16	1		T2	624		T3	4
valid_sources[0x4f]	15303	1			T19	1		T2	716		T3	4
valid_sources[0x50]	17715	1			T2	563		T3	6		T8	2
valid_sources[0x51]	14546	1			T22	1		T16	3		T2	668
valid_sources[0x52]	17216	1			T4	1		T7	1		T2	598
valid_sources[0x53]	16300	1			T16	3		T2	731		T3	2
valid_sources[0x54]	16161	1			T16	4		T2	739		T3	4
valid_sources[0x55]	16147	1			T2	655		T3	4		T80	4
valid_sources[0x56]	15942	1			T22	1		T16	2		T2	728
valid_sources[0x57]	16127	1			T2	734		T3	7		T8	9
valid_sources[0x58]	17492	1			T15	1		T16	1		T2	737
valid_sources[0x59]	16653	1			T22	3		T16	2		T2	707
valid_sources[0x5a]	17626	1			T4	1		T2	737		T3	4
valid_sources[0x5b]	15974	1			T16	1		T2	774		T3	7
valid_sources[0x5c]	17830	1			T16	1		T2	603		T25	4
valid_sources[0x5d]	18131	1			T2	607		T25	2		T3	4
valid_sources[0x5e]	16238	1			T16	1		T2	554		T3	5
valid_sources[0x5f]	16279	1			T4	19		T2	580		T3	6
valid_sources[0x60]	16408	1			T16	3		T2	758		T3	2
valid_sources[0x61]	18322	1			T4	2		T15	1		T2	641
valid_sources[0x62]	15986	1			T2	547		T25	2		T3	3
valid_sources[0x63]	17048	1			T2	596		T3	6		T137	1
valid_sources[0x64]	14245	1			T16	1		T2	710		T3	6
valid_sources[0x65]	15258	1			T16	1		T2	662		T25	1
valid_sources[0x66]	17156	1			T16	2		T19	2		T2	729
valid_sources[0x67]	17402	1			T22	4		T2	622		T3	2
valid_sources[0x68]	15283	1			T2	628		T3	2		T8	5
valid_sources[0x69]	16260	1			T16	2		T2	747		T3	4
valid_sources[0x6a]	16733	1			T2	642		T3	4		T8	2
valid_sources[0x6b]	15795	1			T16	3		T19	1		T2	672
valid_sources[0x6c]	15295	1			T4	3		T16	1		T2	611
valid_sources[0x6d]	16087	1			T6	13		T2	716		T3	1
valid_sources[0x6e]	15932	1			T2	740		T3	4		T166	1
valid_sources[0x6f]	15141	1			T16	1		T2	661		T3	8
valid_sources[0x70]	15974	1			T4	2		T2	736		T3	3
valid_sources[0x71]	16587	1			T16	2		T2	699		T3	2
valid_sources[0x72]	16554	1			T16	1		T2	695		T3	1
valid_sources[0x73]	17144	1			T16	1		T2	627		T25	3
valid_sources[0x74]	16795	1			T22	1		T16	2		T2	533
valid_sources[0x75]	16548	1			T4	8		T2	664		T3	4
valid_sources[0x76]	16288	1			T16	1		T2	616		T3	4
valid_sources[0x77]	15084	1			T4	29		T2	566		T3	7
valid_sources[0x78]	16661	1			T7	6		T16	2		T2	647
valid_sources[0x79]	16796	1			T2	628		T25	3		T3	6
valid_sources[0x7a]	16494	1			T4	22		T2	693		T3	3
valid_sources[0x7b]	17224	1			T16	3		T2	646		T3	2
valid_sources[0x7c]	15796	1			T16	1		T2	744		T3	5
valid_sources[0x7d]	15536	1			T16	1		T2	674		T3	2
valid_sources[0x7e]	15810	1			T16	1		T2	719		T25	5
valid_sources[0x7f]	16442	1			T16	1		T2	707		T3	3
valid_sources[0x80]	17658	1			T2	631		T21	9		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

893977

1

T6

9

T4

3

T7

10

values[0x0]

all_enables

biggest_size

1349578

1

T6

6

T4

82

T7

3

values[0x1]

all_enables

biggest_size

1302501

1

T4

47

T7

2

T22

1