Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T3
0	1	Covered	T19,T2,T3
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T3
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1031236111	15384	0	0
GateOpen_A	1031236111	21955	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031236111	15384	0	0
T2	2329509	339	0	0
T3	744037	27	0	0
T8	428412	0	0	0
T9	0	48	0	0
T19	4259	37	0	0
T20	6399	0	0	0
T21	4129	0	0	0
T25	5664	0	0	0
T26	6781	0	0	0
T27	6275	0	0	0
T28	40423	0	0	0
T29	0	4	0	0
T39	0	20	0	0
T40	0	7	0	0
T41	0	19	0	0
T159	0	10	0	0
T165	0	25	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031236111	21955	0	0
T1	171980	4	0	0
T2	0	364	0	0
T4	242604	0	0	0
T5	242076	0	0	0
T6	20806	4	0	0
T7	12125	4	0	0
T15	13451	4	0	0
T16	428356	0	0	0
T17	15886	0	0	0
T18	3414	4	0	0
T19	0	41	0	0
T20	0	4	0	0
T21	0	4	0	0
T22	5115	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T3
0	1	Covered	T19,T2,T3
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T3
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	114054174	3660	0	0
GateOpen_A	114054174	5301	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114054174	3660	0	0
T2	426760	79	0	0
T3	82671	7	0	0
T8	47590	0	0	0
T9	0	10	0	0
T19	451	10	0	0
T20	689	0	0	0
T21	478	0	0	0
T25	621	0	0	0
T26	736	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T159	0	2	0	0
T165	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114054174	5301	0	0
T1	19100	1	0	0
T2	0	85	0	0
T4	26296	0	0	0
T5	24973	0	0	0
T6	2557	1	0	0
T7	1510	1	0	0
T15	1549	1	0	0
T16	46295	0	0	0
T17	1759	0	0	0
T18	360	1	0	0
T19	0	11	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	551	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T3
0	1	Covered	T19,T2,T3
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T3
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	228109066	3934	0	0
GateOpen_A	228109066	5575	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228109066	3934	0	0
T2	853522	89	0	0
T3	165341	7	0	0
T8	95180	0	0	0
T9	0	13	0	0
T19	902	10	0	0
T20	1377	0	0	0
T21	958	0	0	0
T25	1241	0	0	0
T26	1471	0	0	0
T27	1444	0	0	0
T28	9779	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T159	0	2	0	0
T165	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228109066	5575	0	0
T1	38200	1	0	0
T2	0	95	0	0
T4	52591	0	0	0
T5	49946	0	0	0
T6	5116	1	0	0
T7	3025	1	0	0
T15	3099	1	0	0
T16	92589	0	0	0
T17	3518	0	0	0
T18	719	1	0	0
T19	0	11	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	1101	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T3
0	1	Covered	T19,T2,T3
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T3
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	455653780	3911	0	0
GateOpen_A	455653780	5554	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455653780	3911	0	0
T2	170744	87	0	0
T3	330678	6	0	0
T8	190425	0	0	0
T9	0	13	0	0
T19	1937	9	0	0
T20	2889	0	0	0
T21	1795	0	0	0
T25	2535	0	0	0
T26	3049	0	0	0
T27	2740	0	0	0
T28	17170	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T159	0	2	0	0
T165	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455653780	5554	0	0
T1	76452	1	0	0
T2	0	93	0	0
T4	105303	0	0	0
T5	99916	0	0	0
T6	8755	1	0	0
T7	5060	1	0	0
T15	5868	1	0	0
T16	185298	0	0	0
T17	7072	0	0	0
T18	1557	1	0	0
T19	0	10	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	2308	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T3
0	1	Covered	T19,T2,T3
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T3
1	0	Covered	T39,T40,T41
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	233419091	3879	0	0
GateOpen_A	233419091	5525	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233419091	3879	0	0
T2	878483	84	0	0
T3	165347	7	0	0
T8	95217	0	0	0
T9	0	12	0	0
T19	969	8	0	0
T20	1444	0	0	0
T21	898	0	0	0
T25	1267	0	0	0
T26	1525	0	0	0
T27	1369	0	0	0
T28	8585	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	1	0	0
T41	0	4	0	0
T159	0	4	0	0
T165	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233419091	5525	0	0
T1	38228	1	0	0
T2	0	91	0	0
T4	58414	0	0	0
T5	67241	0	0	0
T6	4378	1	0	0
T7	2530	1	0	0
T15	2935	1	0	0
T16	104174	0	0	0
T17	3537	0	0	0
T18	778	1	0	0
T19	0	9	0	0
T20	0	1	0	0
T21	0	1	0	0
T22	1155	1	0	0