Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	757408805	79884	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	757408805	79884	0	0
T1	350400	84	0	0
T2	2302675	1059	0	0
T3	0	539	0	0
T5	730405	0	0	0
T8	0	145	0	0
T9	0	295	0	0
T10	0	205	0	0
T11	0	419	0	0
T12	0	1738	0	0
T13	0	203	0	0
T14	0	140	0	0
T15	4275	0	0	0
T16	229020	0	0	0
T17	8835	0	0	0
T18	7705	0	0	0
T19	9890	0	0	0
T20	5110	0	0	0
T21	9350	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151481761	11848	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	11848	0	0
T1	70080	11	0	0
T2	460535	167	0	0
T3	0	78	0	0
T5	146081	0	0	0
T8	0	22	0	0
T9	0	43	0	0
T10	0	33	0	0
T11	0	67	0	0
T12	0	226	0	0
T13	0	29	0	0
T14	0	28	0	0
T15	855	0	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T19	1978	0	0	0
T20	1022	0	0	0
T21	1870	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151481761	11573	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	11573	0	0
T1	70080	11	0	0
T2	460535	164	0	0
T3	0	78	0	0
T5	146081	0	0	0
T8	0	22	0	0
T9	0	37	0	0
T10	0	32	0	0
T11	0	65	0	0
T12	0	252	0	0
T13	0	29	0	0
T14	0	28	0	0
T15	855	0	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T19	1978	0	0	0
T20	1022	0	0	0
T21	1870	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151481761	16101	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	16101	0	0
T1	70080	17	0	0
T2	460535	216	0	0
T3	0	107	0	0
T5	146081	0	0	0
T8	0	29	0	0
T9	0	59	0	0
T10	0	42	0	0
T11	0	85	0	0
T12	0	340	0	0
T13	0	41	0	0
T14	0	28	0	0
T15	855	0	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T19	1978	0	0	0
T20	1022	0	0	0
T21	1870	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151481761	16050	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	16050	0	0
T1	70080	17	0	0
T2	460535	214	0	0
T3	0	110	0	0
T5	146081	0	0	0
T8	0	31	0	0
T9	0	61	0	0
T10	0	42	0	0
T11	0	85	0	0
T12	0	346	0	0
T13	0	41	0	0
T14	0	28	0	0
T15	855	0	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T19	1978	0	0	0
T20	1022	0	0	0
T21	1870	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	151481761	24312	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	24312	0	0
T1	70080	28	0	0
T2	460535	298	0	0
T3	0	166	0	0
T5	146081	0	0	0
T8	0	41	0	0
T9	0	95	0	0
T10	0	56	0	0
T11	0	117	0	0
T12	0	574	0	0
T13	0	63	0	0
T14	0	28	0	0
T15	855	0	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T19	1978	0	0	0
T20	1022	0	0	0
T21	1870	0	0	0