Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T2,T3,T30

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	151481761	148821850	0	0
AllClkBypReqTrue_A	151481761	120714	0	0
IoClkBypReqFalse_A	151481761	148749876	0	2415
IoClkBypReqTrue_A	151481761	188078	0	0
LcClkBypAckFalse_A	151481761	148833568	0	0
LcClkBypAckTrue_A	151481761	108996	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	148821850	0	0
T1	70080	69993	0	0
T4	128341	128095	0	0
T5	146081	146025	0	0
T6	2188	1735	0	0
T7	1317	1080	0	0
T15	855	694	0	0
T16	45804	45758	0	0
T17	1767	1723	0	0
T18	1541	1380	0	0
T22	2404	2205	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	120714	0	0
T1	70080	0	0	0
T2	0	1412	0	0
T3	0	104	0	0
T4	128341	0	0	0
T5	146081	0	0	0
T6	2188	419	0	0
T7	1317	183	0	0
T15	855	137	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T21	0	181	0	0
T22	2404	0	0	0
T28	0	140	0	0
T80	0	457	0	0
T105	0	50	0	0
T106	0	63	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	148749876	0	2415
T1	70080	69991	0	3
T4	128341	128093	0	3
T5	146081	146023	0	3
T6	2188	1498	0	3
T7	1317	1083	0	3
T15	855	703	0	3
T16	45804	45756	0	3
T17	1767	1721	0	3
T18	1541	1378	0	3
T22	2404	2203	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	188078	0	0
T1	70080	0	0	0
T2	0	2095	0	0
T3	0	181	0	0
T4	128341	0	0	0
T5	146081	0	0	0
T6	2188	654	0	0
T7	1317	178	0	0
T15	855	126	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T21	0	250	0	0
T22	2404	0	0	0
T27	0	125	0	0
T28	0	244	0	0
T80	0	567	0	0
T106	0	63	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	148833568	0	0
T1	70080	69993	0	0
T4	128341	128095	0	0
T5	146081	146025	0	0
T6	2188	1818	0	0
T7	1317	1169	0	0
T15	855	785	0	0
T16	45804	45758	0	0
T17	1767	1723	0	0
T18	1541	1380	0	0
T22	2404	2205	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	108996	0	0
T1	70080	0	0	0
T2	0	1276	0	0
T3	0	167	0	0
T4	128341	0	0	0
T5	146081	0	0	0
T6	2188	336	0	0
T7	1317	94	0	0
T15	855	46	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T21	0	183	0	0
T22	2404	0	0	0
T27	0	86	0	0
T28	0	129	0	0
T80	0	210	0	0
T106	0	29	0	0