Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1945151048	16077	0	0
TransStop_A	1945151048	8144	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1945151048	16077	0	0
T1	318564	0	0	0
T2	728936	246	0	0
T3	0	46	0	0
T5	584328	0	0	0
T9	0	52	0	0
T11	0	59	0	0
T12	0	301	0	0
T15	24452	0	0	0
T16	820100	0	0	0
T17	29472	12	0	0
T18	6488	0	0	0
T19	8072	0	0	0
T20	12040	0	0	0
T22	9620	23	0	0
T25	0	24	0	0
T26	0	32	0	0
T29	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1945151048	8144	0	0
T1	318564	0	0	0
T2	728936	127	0	0
T3	0	20	0	0
T5	584328	0	0	0
T9	0	32	0	0
T11	0	39	0	0
T12	0	165	0	0
T15	24452	0	0	0
T16	820100	0	0	0
T17	29472	9	0	0
T18	6488	0	0	0
T19	8072	0	0	0
T20	12040	0	0	0
T22	9620	16	0	0
T25	0	8	0	0
T26	0	19	0	0
T29	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486287762	3970	0	0
TransStop_A	486287762	2000	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	3970	0	0
T1	79641	0	0	0
T2	182234	63	0	0
T3	0	12	0	0
T5	146082	0	0	0
T9	0	10	0	0
T11	0	15	0	0
T12	0	74	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	4	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	5	0	0
T25	0	8	0	0
T26	0	10	0	0
T29	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	2000	0	0
T1	79641	0	0	0
T2	182234	30	0	0
T3	0	6	0	0
T5	146082	0	0	0
T9	0	7	0	0
T11	0	10	0	0
T12	0	43	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	4	0	0
T25	0	3	0	0
T26	0	5	0	0
T29	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486287762	4066	0	0
TransStop_A	486287762	2047	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	4066	0	0
T1	79641	0	0	0
T2	182234	63	0	0
T3	0	12	0	0
T5	146082	0	0	0
T9	0	13	0	0
T11	0	13	0	0
T12	0	85	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	7	0	0
T25	0	7	0	0
T26	0	8	0	0
T29	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	2047	0	0
T1	79641	0	0	0
T2	182234	32	0	0
T3	0	3	0	0
T5	146082	0	0	0
T9	0	7	0	0
T11	0	7	0	0
T12	0	46	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	5	0	0
T25	0	1	0	0
T26	0	6	0	0
T29	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486287762	4036	0	0
TransStop_A	486287762	2035	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	4036	0	0
T1	79641	0	0	0
T2	182234	61	0	0
T3	0	11	0	0
T5	146082	0	0	0
T9	0	17	0	0
T11	0	16	0	0
T12	0	63	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	7	0	0
T25	0	8	0	0
T26	0	7	0	0
T29	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	2035	0	0
T1	79641	0	0	0
T2	182234	34	0	0
T3	0	4	0	0
T5	146082	0	0	0
T9	0	11	0	0
T11	0	12	0	0
T12	0	36	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	4	0	0
T25	0	3	0	0
T26	0	5	0	0
T29	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	486287762	4005	0	0
TransStop_A	486287762	2062	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	4005	0	0
T1	79641	0	0	0
T2	182234	59	0	0
T3	0	11	0	0
T5	146082	0	0	0
T9	0	12	0	0
T11	0	15	0	0
T12	0	79	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	4	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	4	0	0
T25	0	1	0	0
T26	0	7	0	0
T29	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287762	2062	0	0
T1	79641	0	0	0
T2	182234	31	0	0
T3	0	7	0	0
T5	146082	0	0	0
T9	0	7	0	0
T11	0	10	0	0
T12	0	40	0	0
T15	6113	0	0	0
T16	205025	0	0	0
T17	7368	3	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3010	0	0	0
T22	2405	3	0	0
T25	0	1	0	0
T26	0	3	0	0
T29	0	1	0	0