Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT6,T4,T7
10CoveredT6,T7,T15 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT6,T7,T15
11CoveredT6,T7,T15 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T7,T15
10CoveredT6,T4,T7
11CoveredT6,T4,T7
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 568911660 568909245 0 0
selKnown1 1366960029 1366957614 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 568911660 568909245 0 0
T1 95500 95497 0 0
T4 131477 131474 0 0
T5 124863 124860 0 0
T6 12017 12014 0 0
T7 7011 7008 0 0
T15 7526 7523 0 0
T16 231472 231469 0 0
T17 8793 8790 0 0
T18 1795 1792 0 0
T22 2752 2749 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1366960029 1366957614 0 0
T1 229353 229350 0 0
T4 315906 315903 0 0
T5 299745 299742 0 0
T6 26265 26262 0 0
T7 15177 15174 0 0
T15 17601 17598 0 0
T16 555894 555891 0 0
T17 21216 21213 0 0
T18 4671 4668 0 0
T22 6924 6921 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT6,T4,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T4,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T4,T7
11CoveredT6,T4,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 228108682 228107877 0 0
selKnown1 455653343 455652538 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 228108682 228107877 0 0
T1 38200 38199 0 0
T4 52591 52590 0 0
T5 49945 49944 0 0
T6 5116 5115 0 0
T7 3025 3024 0 0
T15 3098 3097 0 0
T16 92589 92588 0 0
T17 3517 3516 0 0
T18 718 717 0 0
T22 1101 1100 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 455653343 455652538 0 0
T1 76451 76450 0 0
T4 105302 105301 0 0
T5 99915 99914 0 0
T6 8755 8754 0 0
T7 5059 5058 0 0
T15 5867 5866 0 0
T16 185298 185297 0 0
T17 7072 7071 0 0
T18 1557 1556 0 0
T22 2308 2307 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT6,T4,T7
10CoveredT6,T7,T15 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT6,T7,T15
11CoveredT6,T7,T15 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T7,T15
10CoveredT6,T4,T7
11CoveredT6,T4,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 226749219 226748414 0 0
selKnown1 455653343 455652538 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 226749219 226748414 0 0
T1 38200 38199 0 0
T4 52591 52590 0 0
T5 49945 49944 0 0
T6 4345 4344 0 0
T7 2476 2475 0 0
T15 2880 2879 0 0
T16 92589 92588 0 0
T17 3517 3516 0 0
T18 718 717 0 0
T22 1101 1100 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 455653343 455652538 0 0
T1 76451 76450 0 0
T4 105302 105301 0 0
T5 99915 99914 0 0
T6 8755 8754 0 0
T7 5059 5058 0 0
T15 5867 5866 0 0
T16 185298 185297 0 0
T17 7072 7071 0 0
T18 1557 1556 0 0
T22 2308 2307 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT6,T4,T7
01CoveredT6,T4,T7
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT6,T4,T7
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT6,T4,T7
11CoveredT6,T4,T7
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 114053759 114052954 0 0
selKnown1 455653343 455652538 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 114053759 114052954 0 0
T1 19100 19099 0 0
T4 26295 26294 0 0
T5 24973 24972 0 0
T6 2556 2555 0 0
T7 1510 1509 0 0
T15 1548 1547 0 0
T16 46294 46293 0 0
T17 1759 1758 0 0
T18 359 358 0 0
T22 550 549 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 455653343 455652538 0 0
T1 76451 76450 0 0
T4 105302 105301 0 0
T5 99915 99914 0 0
T6 8755 8754 0 0
T7 5059 5058 0 0
T15 5867 5866 0 0
T16 185298 185297 0 0
T17 7072 7071 0 0
T18 1557 1556 0 0
T22 2308 2307 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%