Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	151481761	18063207	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	18063207	0	60
T1	70080	11643	0	1
T2	460535	763163	0	0
T3	0	49032	0	0
T5	146081	0	0	0
T8	0	10729	0	1
T9	0	36318	0	0
T10	0	13709	0	1
T11	0	26999	0	0
T12	0	826257	0	0
T13	0	19473	0	1
T15	855	0	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T19	1978	0	0	0
T20	1022	0	0	0
T21	1870	0	0	0
T24	0	0	0	1
T31	0	903	0	1
T32	0	0	0	1
T52	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1