Line Coverage for Module :
clkmgr_extclk_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 34 | 1 | 1 | 100.00 |
ALWAYS | 49 | 1 | 1 | 100.00 |
ALWAYS | 66 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
49 |
1 |
1 |
66 |
1 |
1 |
Cond Coverage for Module :
clkmgr_extclk_sva_if
| Total | Covered | Percent |
Conditions | 19 | 19 | 100.00 |
Logical | 19 | 19 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (lc_clk_byp_req_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T6,T7,T15 |
1 | Covered | T6,T7,T15 |
LINE 49
EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
---------------1-------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T6,T7,T15 |
1 | 0 | Covered | T6,T7,T2 |
1 | 1 | Covered | T6,T7,T15 |
LINE 49
SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T15 |
1 | Covered | T6,T7,T15 |
LINE 49
SUB-EXPRESSION (lc_hw_debug_en_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T6,T7,T2 |
1 | Covered | T6,T7,T15 |
LINE 66
EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
---------------1-------------- -------------------2------------------- ------------3-----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T28 |
1 | 0 | 1 | Covered | T6,T7,T2 |
1 | 1 | 0 | Covered | T6,T7,T2 |
1 | 1 | 1 | Covered | T6,T7,T15 |
LINE 66
SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T15 |
1 | Covered | T6,T7,T15 |
LINE 66
SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T15 |
1 | Covered | T6,T7,T15 |
LINE 66
SUB-EXPRESSION (lc_hw_debug_en_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T6,T7,T2 |
1 | Covered | T6,T7,T15 |
Assert Coverage for Module :
clkmgr_extclk_sva_if
Assertion Details
AllClkBypReqFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151481761 |
4010 |
0 |
0 |
T1 |
70080 |
0 |
0 |
0 |
T2 |
0 |
59 |
0 |
0 |
T3 |
0 |
4 |
0 |
0 |
T4 |
128341 |
0 |
0 |
0 |
T5 |
146081 |
0 |
0 |
0 |
T6 |
2188 |
11 |
0 |
0 |
T7 |
1317 |
9 |
0 |
0 |
T15 |
855 |
3 |
0 |
0 |
T16 |
45804 |
0 |
0 |
0 |
T17 |
1767 |
0 |
0 |
0 |
T18 |
1541 |
0 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T22 |
2404 |
0 |
0 |
0 |
T28 |
0 |
5 |
0 |
0 |
T80 |
0 |
14 |
0 |
0 |
T105 |
0 |
3 |
0 |
0 |
T106 |
0 |
10 |
0 |
0 |
AllClkBypReqRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151481761 |
4010 |
0 |
0 |
T1 |
70080 |
0 |
0 |
0 |
T2 |
0 |
59 |
0 |
0 |
T3 |
0 |
4 |
0 |
0 |
T4 |
128341 |
0 |
0 |
0 |
T5 |
146081 |
0 |
0 |
0 |
T6 |
2188 |
11 |
0 |
0 |
T7 |
1317 |
9 |
0 |
0 |
T15 |
855 |
3 |
0 |
0 |
T16 |
45804 |
0 |
0 |
0 |
T17 |
1767 |
0 |
0 |
0 |
T18 |
1541 |
0 |
0 |
0 |
T21 |
0 |
5 |
0 |
0 |
T22 |
2404 |
0 |
0 |
0 |
T28 |
0 |
5 |
0 |
0 |
T80 |
0 |
14 |
0 |
0 |
T105 |
0 |
3 |
0 |
0 |
T106 |
0 |
10 |
0 |
0 |
HiSpeedSelFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151481761 |
2430 |
0 |
0 |
T1 |
70080 |
0 |
0 |
0 |
T2 |
0 |
36 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T4 |
128341 |
0 |
0 |
0 |
T5 |
146081 |
0 |
0 |
0 |
T6 |
2188 |
10 |
0 |
0 |
T7 |
1317 |
8 |
0 |
0 |
T15 |
855 |
3 |
0 |
0 |
T16 |
45804 |
0 |
0 |
0 |
T17 |
1767 |
0 |
0 |
0 |
T18 |
1541 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T22 |
2404 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T105 |
0 |
1 |
0 |
0 |
T106 |
0 |
8 |
0 |
0 |
HiSpeedSelRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151481761 |
2430 |
0 |
0 |
T1 |
70080 |
0 |
0 |
0 |
T2 |
0 |
36 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T4 |
128341 |
0 |
0 |
0 |
T5 |
146081 |
0 |
0 |
0 |
T6 |
2188 |
10 |
0 |
0 |
T7 |
1317 |
8 |
0 |
0 |
T15 |
855 |
3 |
0 |
0 |
T16 |
45804 |
0 |
0 |
0 |
T17 |
1767 |
0 |
0 |
0 |
T18 |
1541 |
0 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T22 |
2404 |
0 |
0 |
0 |
T28 |
0 |
2 |
0 |
0 |
T80 |
0 |
4 |
0 |
0 |
T105 |
0 |
1 |
0 |
0 |
T106 |
0 |
8 |
0 |
0 |
IoClkBypReqFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151481761 |
4862 |
0 |
0 |
T1 |
70080 |
0 |
0 |
0 |
T2 |
0 |
67 |
0 |
0 |
T3 |
0 |
4 |
0 |
0 |
T4 |
128341 |
0 |
0 |
0 |
T5 |
146081 |
0 |
0 |
0 |
T6 |
2188 |
15 |
0 |
0 |
T7 |
1317 |
6 |
0 |
0 |
T15 |
855 |
3 |
0 |
0 |
T16 |
45804 |
0 |
0 |
0 |
T17 |
1767 |
0 |
0 |
0 |
T18 |
1541 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
2404 |
0 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T80 |
0 |
15 |
0 |
0 |
T106 |
0 |
2 |
0 |
0 |
IoClkBypReqRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
151481761 |
4861 |
0 |
0 |
T1 |
70080 |
0 |
0 |
0 |
T2 |
0 |
67 |
0 |
0 |
T3 |
0 |
4 |
0 |
0 |
T4 |
128341 |
0 |
0 |
0 |
T5 |
146081 |
0 |
0 |
0 |
T6 |
2188 |
15 |
0 |
0 |
T7 |
1317 |
6 |
0 |
0 |
T15 |
855 |
3 |
0 |
0 |
T16 |
45804 |
0 |
0 |
0 |
T17 |
1767 |
0 |
0 |
0 |
T18 |
1541 |
0 |
0 |
0 |
T21 |
0 |
6 |
0 |
0 |
T22 |
2404 |
0 |
0 |
0 |
T27 |
0 |
4 |
0 |
0 |
T28 |
0 |
6 |
0 |
0 |
T80 |
0 |
15 |
0 |
0 |
T106 |
0 |
2 |
0 |
0 |