Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	152375875	5168411	0	0
clk_enables_rd_A	152375875	26207	0	0
clk_hints_rd_A	152375875	22659	0	0
extclk_ctrl_rd_A	152375875	28034	0	0
extclk_ctrl_regwen_rd_A	152375875	21005	0	0
jitter_enable_rd_A	152375875	32607	0	0
jitter_regwen_rd_A	152375875	24400	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152375875	5168411	0	0
T2	460535	225190	0	0
T3	172233	0	0	0
T8	51573	0	0	0
T12	0	178891	0	0
T20	1022	0	0	0
T21	1870	0	0	0
T25	2508	0	0	0
T26	3175	0	0	0
T27	1426	0	0	0
T28	1252	0	0	0
T29	1960	0	0	0
T42	0	55164	0	0
T64	0	152640	0	0
T65	0	278525	0	0
T66	0	131471	0	0
T67	0	85032	0	0
T68	0	151896	0	0
T69	0	111744	0	0
T70	0	90410	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152375875	26207	0	0
T23	74698	13	0	0
T36	0	4280	0	0
T42	0	1908	0	0
T43	8365	0	0	0
T48	1320	0	0	0
T49	1226	0	0	0
T50	1804	0	0	0
T64	0	6232	0	0
T72	15452	0	0	0
T125	0	15	0	0
T126	0	2	0	0
T127	0	871	0	0
T128	0	1515	0	0
T129	0	8	0	0
T130	0	1	0	0
T131	3873	0	0	0
T132	1255	0	0	0
T133	1501	0	0	0
T134	1403	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152375875	22659	0	0
T23	74698	11	0	0
T42	0	1743	0	0
T43	8365	0	0	0
T48	1320	0	0	0
T49	1226	0	0	0
T50	1804	0	0	0
T64	0	5142	0	0
T72	15452	0	0	0
T125	0	9	0	0
T126	0	2	0	0
T127	0	722	0	0
T128	0	1111	0	0
T129	0	14	0	0
T131	3873	0	0	0
T132	1255	0	0	0
T133	1501	0	0	0
T134	1403	0	0	0
T135	0	3	0	0
T136	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152375875	28034	0	0
T1	70080	0	0	0
T4	128341	0	0	0
T5	146081	0	0	0
T6	2188	52	0	0
T7	1317	0	0	0
T15	855	4	0	0
T16	45804	0	0	0
T17	1767	0	0	0
T18	1541	0	0	0
T21	0	16	0	0
T22	2404	0	0	0
T71	0	79	0	0
T133	0	20	0	0
T137	0	67	0	0
T138	0	5	0	0
T139	0	5	0	0
T140	0	31	0	0
T141	0	19	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152375875	21005	0	0
T11	241968	0	0	0
T12	374570	0	0	0
T13	110437	0	0	0
T31	26751	0	0	0
T36	0	3631	0	0
T42	0	1850	0	0
T64	0	5257	0	0
T71	22407	36	0	0
T127	0	722	0	0
T128	0	1079	0	0
T142	0	25	0	0
T143	0	33	0	0
T144	0	50	0	0
T145	0	1315	0	0
T146	1212	0	0	0
T147	1928	0	0	0
T148	245306	0	0	0
T149	1557	0	0	0
T150	3117	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152375875	32607	0	0
T23	74698	518	0	0
T42	0	2414	0	0
T43	8365	0	0	0
T48	1320	0	0	0
T49	1226	0	0	0
T50	1804	0	0	0
T64	0	6521	0	0
T72	15452	0	0	0
T125	0	278	0	0
T126	0	80	0	0
T127	0	898	0	0
T128	0	2056	0	0
T129	0	259	0	0
T131	3873	0	0	0
T132	1255	0	0	0
T133	1501	0	0	0
T134	1403	0	0	0
T135	0	122	0	0
T136	0	60	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152375875	24400	0	0
T36	0	4496	0	0
T42	185584	2068	0	0
T64	512051	6148	0	0
T74	0	13	0	0
T83	2350	0	0	0
T84	1638	0	0	0
T102	31008	0	0	0
T127	0	888	0	0
T128	0	1280	0	0
T145	0	1512	0	0
T151	0	3493	0	0
T152	0	2313	0	0
T153	0	10	0	0
T154	1045	0	0	0
T155	2198	0	0	0
T156	1196	0	0	0
T157	1188	0	0	0
T158	76617	0	0	0