Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT6,T7,T15
11CoveredT6,T7,T15

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 455653780 4155 0 0
g_div2.Div2Whole_A 455653780 4974 0 0
g_div4.Div4Stepped_A 228109066 4075 0 0
g_div4.Div4Whole_A 228109066 4698 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 455653780 4155 0 0
T1 76452 0 0 0
T2 0 60 0 0
T3 0 6 0 0
T4 105303 0 0 0
T5 99916 0 0 0
T6 8755 13 0 0
T7 5060 8 0 0
T15 5868 2 0 0
T16 185298 0 0 0
T17 7072 0 0 0
T18 1557 0 0 0
T21 0 5 0 0
T22 2308 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 10 0 0
T106 0 4 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 455653780 4974 0 0
T1 76452 0 0 0
T2 0 69 0 0
T3 0 6 0 0
T4 105303 0 0 0
T5 99916 0 0 0
T6 8755 14 0 0
T7 5060 8 0 0
T15 5868 2 0 0
T16 185298 0 0 0
T17 7072 0 0 0
T18 1557 0 0 0
T21 0 5 0 0
T22 2308 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 10 0 0
T105 0 3 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228109066 4075 0 0
T1 38200 0 0 0
T2 0 60 0 0
T3 0 6 0 0
T4 52591 0 0 0
T5 49946 0 0 0
T6 5116 13 0 0
T7 3025 8 0 0
T15 3099 2 0 0
T16 92589 0 0 0
T17 3518 0 0 0
T18 719 0 0 0
T21 0 5 0 0
T22 1101 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 10 0 0
T106 0 4 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228109066 4698 0 0
T1 38200 0 0 0
T2 0 69 0 0
T3 0 6 0 0
T4 52591 0 0 0
T5 49946 0 0 0
T6 5116 14 0 0
T7 3025 8 0 0
T15 3099 2 0 0
T16 92589 0 0 0
T17 3518 0 0 0
T18 719 0 0 0
T21 0 4 0 0
T22 1101 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 9 0 0
T105 0 3 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT6,T7,T15
11CoveredT6,T7,T15

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 455653780 4155 0 0
g_div2.Div2Whole_A 455653780 4974 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 455653780 4155 0 0
T1 76452 0 0 0
T2 0 60 0 0
T3 0 6 0 0
T4 105303 0 0 0
T5 99916 0 0 0
T6 8755 13 0 0
T7 5060 8 0 0
T15 5868 2 0 0
T16 185298 0 0 0
T17 7072 0 0 0
T18 1557 0 0 0
T21 0 5 0 0
T22 2308 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 10 0 0
T106 0 4 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 455653780 4974 0 0
T1 76452 0 0 0
T2 0 69 0 0
T3 0 6 0 0
T4 105303 0 0 0
T5 99916 0 0 0
T6 8755 14 0 0
T7 5060 8 0 0
T15 5868 2 0 0
T16 185298 0 0 0
T17 7072 0 0 0
T18 1557 0 0 0
T21 0 5 0 0
T22 2308 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 10 0 0
T105 0 3 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT6,T4,T7
10CoveredT6,T7,T15
11CoveredT6,T7,T15

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 228109066 4075 0 0
g_div4.Div4Whole_A 228109066 4698 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228109066 4075 0 0
T1 38200 0 0 0
T2 0 60 0 0
T3 0 6 0 0
T4 52591 0 0 0
T5 49946 0 0 0
T6 5116 13 0 0
T7 3025 8 0 0
T15 3099 2 0 0
T16 92589 0 0 0
T17 3518 0 0 0
T18 719 0 0 0
T21 0 5 0 0
T22 1101 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 10 0 0
T106 0 4 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 228109066 4698 0 0
T1 38200 0 0 0
T2 0 69 0 0
T3 0 6 0 0
T4 52591 0 0 0
T5 49946 0 0 0
T6 5116 14 0 0
T7 3025 8 0 0
T15 3099 2 0 0
T16 92589 0 0 0
T17 3518 0 0 0
T18 719 0 0 0
T21 0 4 0 0
T22 1101 0 0 0
T27 0 3 0 0
T28 0 8 0 0
T80 0 9 0 0
T105 0 3 0 0

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