Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	454445283	476	0	0
StatusRise_A	454445283	476	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454445283	476	0	0
T30	4728	0	0	0
T34	4017	0	0	0
T39	3585	13	0	0
T40	3552	4	0	0
T41	5040	14	0	0
T80	6348	0	0	0
T105	5007	0	0	0
T106	4902	0	0	0
T149	0	12	0	0
T159	0	10	0	0
T160	0	12	0	0
T161	0	13	0	0
T162	0	3	0	0
T163	0	6	0	0
T164	0	13	0	0
T165	3285	0	0	0
T166	5001	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454445283	476	0	0
T30	4728	0	0	0
T34	4017	0	0	0
T39	3585	13	0	0
T40	3552	4	0	0
T41	5040	14	0	0
T80	6348	0	0	0
T105	5007	0	0	0
T106	4902	0	0	0
T149	0	12	0	0
T159	0	10	0	0
T160	0	12	0	0
T161	0	13	0	0
T162	0	3	0	0
T163	0	6	0	0
T164	0	13	0	0
T165	3285	0	0	0
T166	5001	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151481761	160	0	0
StatusRise_A	151481761	160	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	160	0	0
T30	1576	0	0	0
T34	1339	0	0	0
T39	1195	3	0	0
T40	1184	1	0	0
T41	1680	5	0	0
T80	2116	0	0	0
T105	1669	0	0	0
T106	1634	0	0	0
T149	0	5	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	1095	0	0	0
T166	1667	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	160	0	0
T30	1576	0	0	0
T34	1339	0	0	0
T39	1195	3	0	0
T40	1184	1	0	0
T41	1680	5	0	0
T80	2116	0	0	0
T105	1669	0	0	0
T106	1634	0	0	0
T149	0	5	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	1095	0	0	0
T166	1667	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151481761	161	0	0
StatusRise_A	151481761	161	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	161	0	0
T30	1576	0	0	0
T34	1339	0	0	0
T39	1195	5	0	0
T40	1184	2	0	0
T41	1680	5	0	0
T80	2116	0	0	0
T105	1669	0	0	0
T106	1634	0	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	1095	0	0	0
T166	1667	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	161	0	0
T30	1576	0	0	0
T34	1339	0	0	0
T39	1195	5	0	0
T40	1184	2	0	0
T41	1680	5	0	0
T80	2116	0	0	0
T105	1669	0	0	0
T106	1634	0	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	1095	0	0	0
T166	1667	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	151481761	155	0	0
StatusRise_A	151481761	155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	155	0	0
T30	1576	0	0	0
T34	1339	0	0	0
T39	1195	5	0	0
T40	1184	1	0	0
T41	1680	4	0	0
T80	2116	0	0	0
T105	1669	0	0	0
T106	1634	0	0	0
T149	0	4	0	0
T159	0	4	0	0
T160	0	2	0	0
T161	0	5	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	1095	0	0	0
T166	1667	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	151481761	155	0	0
T30	1576	0	0	0
T34	1339	0	0	0
T39	1195	5	0	0
T40	1184	1	0	0
T41	1680	4	0	0
T80	2116	0	0	0
T105	1669	0	0	0
T106	1634	0	0	0
T149	0	4	0	0
T159	0	4	0	0
T160	0	2	0	0
T161	0	5	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	1095	0	0	0
T166	1667	0	0	0