Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	51272	0	0
CgEnOn_A	2147483647	42056	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	51272	0	0
T1	213391	3	0	0
T2	2486776	68	0	0
T3	744032	0	0	0
T4	184188	3	0	0
T5	320914	3	0	0
T6	16427	3	0	0
T7	9594	3	0	0
T8	428374	0	0	0
T12	0	5	0	0
T15	16625	3	0	0
T16	529205	3	0	0
T17	19715	7	0	0
T18	4256	3	0	0
T19	2018	0	0	0
T20	9338	0	0	0
T21	4187	0	0	0
T22	6363	8	0	0
T25	5635	8	0	0
T26	6724	0	0	0
T27	6349	0	0	0
T28	41615	0	0	0
T29	4299	0	0	0
T39	0	28	0	0
T40	0	11	0	0
T41	0	30	0	0
T149	0	15	0	0
T159	0	10	0	0
T160	0	30	0	0
T161	0	20	0	0
T162	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	42056	0	0
T1	159280	0	0	0
T2	4120034	546	0	0
T3	1322722	53	0	0
T5	292162	0	0	0
T8	761568	0	0	0
T9	0	53	0	0
T12	0	4	0	0
T15	12224	0	0	0
T16	410048	0	0	0
T17	14734	6	0	0
T18	3244	0	0	0
T19	7326	44	0	0
T20	17300	0	0	0
T21	7418	0	0	0
T22	4808	12	0	0
T25	10030	15	0	0
T26	11978	18	0	0
T27	11254	0	0	0
T28	73452	0	0	0
T29	4299	5	0	0
T39	5113	49	0	0
T40	0	19	0	0
T41	0	55	0	0
T80	8823	0	0	0
T149	0	20	0	0
T159	0	20	0	0
T160	0	34	0	0
T161	0	24	0	0
T162	0	6	0	0
T163	0	4	0	0
T164	0	4	0	0
T165	5478	25	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228108682	170	0	0
CgEnOn_A	228108682	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228108682	170	0	0
T2	853521	1	0	0
T3	165341	0	0	0
T8	95179	0	0	0
T12	0	1	0	0
T20	1377	0	0	0
T21	958	0	0	0
T25	1241	0	0	0
T26	1471	0	0	0
T27	1444	0	0	0
T28	9779	0	0	0
T29	944	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228108682	170	0	0
T2	853521	1	0	0
T3	165341	0	0	0
T8	95179	0	0	0
T12	0	1	0	0
T20	1377	0	0	0
T21	958	0	0	0
T25	1241	0	0	0
T26	1471	0	0	0
T27	1444	0	0	0
T28	9779	0	0	0
T29	944	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114053759	170	0	0
CgEnOn_A	114053759	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	170	0	0
T2	426759	1	0	0
T3	82671	0	0	0
T8	47590	0	0	0
T12	0	1	0	0
T20	688	0	0	0
T21	478	0	0	0
T25	620	0	0	0
T26	735	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	472	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	170	0	0
T2	426759	1	0	0
T3	82671	0	0	0
T8	47590	0	0	0
T12	0	1	0	0
T20	688	0	0	0
T21	478	0	0	0
T25	620	0	0	0
T26	735	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	472	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114053759	170	0	0
CgEnOn_A	114053759	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	170	0	0
T2	426759	1	0	0
T3	82671	0	0	0
T8	47590	0	0	0
T12	0	1	0	0
T20	688	0	0	0
T21	478	0	0	0
T25	620	0	0	0
T26	735	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	472	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	170	0	0
T2	426759	1	0	0
T3	82671	0	0	0
T8	47590	0	0	0
T12	0	1	0	0
T20	688	0	0	0
T21	478	0	0	0
T25	620	0	0	0
T26	735	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	472	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114053759	170	0	0
CgEnOn_A	114053759	170	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	170	0	0
T2	426759	1	0	0
T3	82671	0	0	0
T8	47590	0	0	0
T12	0	1	0	0
T20	688	0	0	0
T21	478	0	0	0
T25	620	0	0	0
T26	735	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	472	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	170	0	0
T2	426759	1	0	0
T3	82671	0	0	0
T8	47590	0	0	0
T12	0	1	0	0
T20	688	0	0	0
T21	478	0	0	0
T25	620	0	0	0
T26	735	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	472	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455653343	170	0	0
CgEnOn_A	455653343	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455653343	170	0	0
T2	170744	1	0	0
T3	330678	0	0	0
T8	190425	0	0	0
T12	0	1	0	0
T20	2888	0	0	0
T21	1795	0	0	0
T25	2534	0	0	0
T26	3048	0	0	0
T27	2739	0	0	0
T28	17169	0	0	0
T29	1939	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455653343	164	0	0
T2	170744	1	0	0
T3	330678	0	0	0
T8	190425	0	0	0
T20	2888	0	0	0
T21	1795	0	0	0
T25	2534	0	0	0
T26	3048	0	0	0
T27	2739	0	0	0
T28	17169	0	0	0
T29	1939	0	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T149	0	3	0	0
T159	0	2	0	0
T160	0	6	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486287318	163	0	0
CgEnOn_A	486287318	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	163	0	0
T30	12127	0	0	0
T34	1424	0	0	0
T39	5113	3	0	0
T40	2392	1	0	0
T41	1497	5	0	0
T80	8823	0	0	0
T105	1720	0	0	0
T106	6813	0	0	0
T149	0	5	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	5478	0	0	0
T166	3402	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	161	0	0
T30	12127	0	0	0
T34	1424	0	0	0
T39	5113	3	0	0
T40	2392	1	0	0
T41	1497	5	0	0
T80	8823	0	0	0
T105	1720	0	0	0
T106	6813	0	0	0
T149	0	5	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	5478	0	0	0
T166	3402	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486287318	163	0	0
CgEnOn_A	486287318	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	163	0	0
T30	12127	0	0	0
T34	1424	0	0	0
T39	5113	3	0	0
T40	2392	1	0	0
T41	1497	5	0	0
T80	8823	0	0	0
T105	1720	0	0	0
T106	6813	0	0	0
T149	0	5	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	5478	0	0	0
T166	3402	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	161	0	0
T30	12127	0	0	0
T34	1424	0	0	0
T39	5113	3	0	0
T40	2392	1	0	0
T41	1497	5	0	0
T80	8823	0	0	0
T105	1720	0	0	0
T106	6813	0	0	0
T149	0	5	0	0
T159	0	4	0	0
T160	0	4	0	0
T161	0	4	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	4	0	0
T165	5478	0	0	0
T166	3402	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233418674	158	0	0
CgEnOn_A	233418674	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233418674	158	0	0
T30	5820	0	0	0
T34	683	0	0	0
T39	2496	5	0	0
T40	1133	1	0	0
T41	755	4	0	0
T80	4234	0	0	0
T105	826	0	0	0
T106	3270	0	0	0
T149	0	4	0	0
T159	0	4	0	0
T160	0	2	0	0
T161	0	5	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	2629	0	0	0
T166	1633	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233418674	157	0	0
T30	5820	0	0	0
T34	683	0	0	0
T39	2496	5	0	0
T40	1133	1	0	0
T41	755	4	0	0
T80	4234	0	0	0
T105	826	0	0	0
T106	3270	0	0	0
T149	0	4	0	0
T159	0	4	0	0
T160	0	2	0	0
T161	0	5	0	0
T162	0	1	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	2629	0	0	0
T166	1633	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	114053759	8264	0	0
CgEnOn_A	114053759	5968	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	8264	0	0
T1	19100	1	0	0
T4	26295	1	0	0
T5	24973	1	0	0
T6	2556	1	0	0
T7	1510	1	0	0
T15	1548	1	0	0
T16	46294	1	0	0
T17	1759	1	0	0
T18	359	1	0	0
T22	550	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114053759	5968	0	0
T2	426759	138	0	0
T3	82671	10	0	0
T8	47590	0	0	0
T9	0	16	0	0
T19	451	13	0	0
T20	688	0	0	0
T21	478	0	0	0
T25	620	0	0	0
T26	735	0	0	0
T27	722	0	0	0
T28	4889	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T159	0	2	0	0
T165	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	228108682	8339	0	0
CgEnOn_A	228108682	6043	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228108682	8339	0	0
T1	38200	1	0	0
T4	52591	1	0	0
T5	49945	1	0	0
T6	5116	1	0	0
T7	3025	1	0	0
T15	3098	1	0	0
T16	92589	1	0	0
T17	3517	1	0	0
T18	718	1	0	0
T22	1101	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	228108682	6043	0	0
T2	853521	142	0	0
T3	165341	10	0	0
T8	95179	0	0	0
T9	0	18	0	0
T19	902	16	0	0
T20	1377	0	0	0
T21	958	0	0	0
T25	1241	0	0	0
T26	1471	0	0	0
T27	1444	0	0	0
T28	9779	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T159	0	2	0	0
T165	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	455653343	8315	0	0
CgEnOn_A	455653343	6013	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455653343	8315	0	0
T1	76451	1	0	0
T4	105302	1	0	0
T5	99915	1	0	0
T6	8755	1	0	0
T7	5059	1	0	0
T15	5867	1	0	0
T16	185298	1	0	0
T17	7072	1	0	0
T18	1557	1	0	0
T22	2308	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455653343	6013	0	0
T2	170744	135	0	0
T3	330678	9	0	0
T8	190425	0	0	0
T9	0	19	0	0
T19	1937	15	0	0
T20	2888	0	0	0
T21	1795	0	0	0
T25	2534	0	0	0
T26	3048	0	0	0
T27	2739	0	0	0
T28	17169	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	2	0	0
T41	0	5	0	0
T159	0	2	0	0
T165	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T39,T40,T41
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	233418674	8291	0	0
CgEnOn_A	233418674	5988	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233418674	8291	0	0
T1	38227	1	0	0
T4	58414	1	0	0
T5	67240	1	0	0
T6	4377	1	0	0
T7	2530	1	0	0
T15	2934	1	0	0
T16	104173	1	0	0
T17	3536	1	0	0
T18	778	1	0	0
T22	1154	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233418674	5988	0	0
T2	878483	139	0	0
T3	165346	10	0	0
T8	95216	0	0	0
T9	0	16	0	0
T19	968	16	0	0
T20	1444	0	0	0
T21	897	0	0	0
T25	1266	0	0	0
T26	1524	0	0	0
T27	1369	0	0	0
T28	8585	0	0	0
T29	0	1	0	0
T39	0	5	0	0
T40	0	1	0	0
T41	0	4	0	0
T159	0	4	0	0
T165	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Covered	T22,T17,T2
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486287318	4133	0	0
CgEnOn_A	486287318	4131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4133	0	0
T1	79640	0	0	0
T2	182234	63	0	0
T3	0	12	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	4	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	5	0	0
T25	0	8	0	0
T26	0	10	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4131	0	0
T1	79640	0	0	0
T2	182234	63	0	0
T3	0	12	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	4	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	5	0	0
T25	0	8	0	0
T26	0	10	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Covered	T22,T17,T2
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486287318	4229	0	0
CgEnOn_A	486287318	4227	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4229	0	0
T1	79640	0	0	0
T2	182234	63	0	0
T3	0	12	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	7	0	0
T25	0	7	0	0
T26	0	8	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4227	0	0
T1	79640	0	0	0
T2	182234	63	0	0
T3	0	12	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	7	0	0
T25	0	7	0	0
T26	0	8	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Covered	T22,T17,T2
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486287318	4199	0	0
CgEnOn_A	486287318	4197	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4199	0	0
T1	79640	0	0	0
T2	182234	61	0	0
T3	0	11	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	7	0	0
T25	0	8	0	0
T26	0	7	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4197	0	0
T1	79640	0	0	0
T2	182234	61	0	0
T3	0	11	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	2	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	7	0	0
T25	0	8	0	0
T26	0	7	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T39
1	0	Covered	T22,T17,T2
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	486287318	4168	0	0
CgEnOn_A	486287318	4166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4168	0	0
T1	79640	0	0	0
T2	182234	59	0	0
T3	0	11	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	4	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	4	0	0
T25	0	1	0	0
T26	0	7	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486287318	4166	0	0
T1	79640	0	0	0
T2	182234	59	0	0
T3	0	11	0	0
T5	146081	0	0	0
T15	6112	0	0	0
T16	205024	0	0	0
T17	7367	4	0	0
T18	1622	0	0	0
T19	2018	0	0	0
T20	3009	0	0	0
T22	2404	4	0	0
T25	0	1	0	0
T26	0	7	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0