Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	678166	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3856988

1

T4

201

T6

42

T25

44

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1104331	1			T4	240		T6	60		T25	76
values[0x0]	1576080	1			T4	115		T6	22		T25	27
values[0x1]	1854743	1			T4	115		T6	23		T25	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	374132	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4161022

1

T4

276

T6

53

T25

60

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18635	1			T30	2		T31	1		T10	224
valid_sources[0x01]	17759	1			T30	1		T3	2		T10	219
valid_sources[0x02]	18220	1			T17	1		T23	1		T30	2
valid_sources[0x03]	18806	1			T6	2		T17	1		T18	4
valid_sources[0x04]	17812	1			T6	1		T42	1		T3	5
valid_sources[0x05]	18841	1			T5	1		T27	1		T31	1
valid_sources[0x06]	17785	1			T30	3		T10	206		T68	1
valid_sources[0x07]	17704	1			T20	1		T128	1		T102	1
valid_sources[0x08]	17562	1			T19	1		T3	1		T10	175
valid_sources[0x09]	18083	1			T27	1		T20	1		T30	1
valid_sources[0x0a]	16290	1			T19	2		T30	1		T31	1
valid_sources[0x0b]	17645	1			T6	1		T22	2		T30	2
valid_sources[0x0c]	17733	1			T17	1		T30	2		T3	3
valid_sources[0x0d]	18792	1			T30	5		T3	3		T10	224
valid_sources[0x0e]	17180	1			T30	1		T102	1		T3	1
valid_sources[0x0f]	17610	1			T6	1		T25	133		T17	3
valid_sources[0x10]	18156	1			T23	1		T30	7		T42	1
valid_sources[0x11]	17902	1			T6	1		T17	1		T3	1
valid_sources[0x12]	18718	1			T17	2		T31	1		T10	201
valid_sources[0x13]	17441	1			T6	1		T27	1		T18	3
valid_sources[0x14]	17424	1			T6	1		T27	2		T18	1
valid_sources[0x15]	16000	1			T30	6		T3	1		T10	199
valid_sources[0x16]	18329	1			T30	2		T31	2		T94	1
valid_sources[0x17]	17911	1			T6	2		T23	2		T30	8
valid_sources[0x18]	16467	1			T17	2		T30	11		T42	1
valid_sources[0x19]	17974	1			T5	1		T17	2		T22	2
valid_sources[0x1a]	19382	1			T6	1		T21	5		T22	2
valid_sources[0x1b]	18678	1			T6	2		T19	1		T22	1
valid_sources[0x1c]	17703	1			T27	2		T17	1		T102	1
valid_sources[0x1d]	17428	1			T6	1		T17	1		T10	187
valid_sources[0x1e]	16832	1			T6	1		T27	1		T17	1
valid_sources[0x1f]	17353	1			T20	2		T43	2		T94	1
valid_sources[0x20]	17117	1			T17	1		T22	1		T23	4
valid_sources[0x21]	18111	1			T27	2		T94	1		T10	170
valid_sources[0x22]	18802	1			T6	2		T30	1		T3	3
valid_sources[0x23]	17239	1			T5	8		T31	1		T3	6
valid_sources[0x24]	17441	1			T30	2		T31	1		T10	176
valid_sources[0x25]	17427	1			T5	12		T17	1		T31	1
valid_sources[0x26]	18105	1			T17	2		T23	2		T30	1
valid_sources[0x27]	19339	1			T6	1		T5	1		T3	1
valid_sources[0x28]	18569	1			T27	1		T17	1		T127	1
valid_sources[0x29]	18027	1			T27	1		T30	3		T127	1
valid_sources[0x2a]	18919	1			T5	11		T30	1		T3	1
valid_sources[0x2b]	17013	1			T5	2		T27	1		T31	1
valid_sources[0x2c]	17492	1			T6	1		T17	1		T30	4
valid_sources[0x2d]	16608	1			T17	1		T30	1		T3	1
valid_sources[0x2e]	16751	1			T30	4		T10	189		T13	625
valid_sources[0x2f]	17272	1			T30	1		T3	6		T10	204
valid_sources[0x30]	16020	1			T30	4		T94	1		T10	178
valid_sources[0x31]	16431	1			T127	1		T94	1		T3	1
valid_sources[0x32]	18123	1			T17	3		T22	1		T30	1
valid_sources[0x33]	20407	1			T17	3		T94	1		T10	176
valid_sources[0x34]	15804	1			T27	1		T1	124		T17	1
valid_sources[0x35]	18144	1			T17	2		T20	1		T30	1
valid_sources[0x36]	17990	1			T6	2		T27	2		T22	1
valid_sources[0x37]	18165	1			T5	8		T10	168		T70	9
valid_sources[0x38]	18937	1			T17	2		T22	1		T44	49
valid_sources[0x39]	18526	1			T27	1		T23	3		T30	5
valid_sources[0x3a]	16665	1			T6	2		T17	3		T30	1
valid_sources[0x3b]	16228	1			T17	1		T19	3		T30	1
valid_sources[0x3c]	18397	1			T6	1		T17	1		T30	5
valid_sources[0x3d]	17936	1			T6	1		T30	1		T31	1
valid_sources[0x3e]	17728	1			T22	1		T30	1		T31	2
valid_sources[0x3f]	19067	1			T6	1		T27	2		T17	3
valid_sources[0x40]	20652	1			T6	1		T17	1		T30	1
valid_sources[0x41]	17653	1			T27	1		T31	1		T3	1
valid_sources[0x42]	17376	1			T17	2		T42	2		T31	1
valid_sources[0x43]	17321	1			T6	1		T10	211		T12	4
valid_sources[0x44]	17559	1			T30	4		T3	1		T10	195
valid_sources[0x45]	17213	1			T17	1		T31	1		T3	3
valid_sources[0x46]	17825	1			T23	1		T127	1		T10	176
valid_sources[0x47]	16342	1			T30	1		T42	1		T3	2
valid_sources[0x48]	18487	1			T6	1		T23	5		T30	4
valid_sources[0x49]	18210	1			T30	1		T3	3		T10	187
valid_sources[0x4a]	16521	1			T5	5		T23	2		T3	1
valid_sources[0x4b]	18226	1			T27	1		T30	1		T10	225
valid_sources[0x4c]	17027	1			T17	1		T22	1		T23	3
valid_sources[0x4d]	17334	1			T6	1		T17	1		T30	1
valid_sources[0x4e]	18033	1			T6	2		T21	15		T94	1
valid_sources[0x4f]	17737	1			T5	21		T20	2		T30	4
valid_sources[0x50]	16765	1			T17	3		T94	2		T3	1
valid_sources[0x51]	18319	1			T5	2		T30	1		T42	1
valid_sources[0x52]	15665	1			T6	2		T30	1		T42	1
valid_sources[0x53]	17370	1			T30	1		T32	48		T3	2
valid_sources[0x54]	16349	1			T27	1		T30	2		T102	1
valid_sources[0x55]	17657	1			T6	1		T27	1		T17	1
valid_sources[0x56]	17638	1			T6	1		T17	1		T127	1
valid_sources[0x57]	17479	1			T17	1		T22	2		T31	2
valid_sources[0x58]	15671	1			T17	3		T22	3		T30	2
valid_sources[0x59]	16816	1			T94	1		T10	173		T12	1
valid_sources[0x5a]	17872	1			T27	1		T17	1		T30	3
valid_sources[0x5b]	19425	1			T6	2		T22	1		T30	3
valid_sources[0x5c]	16814	1			T3	3		T10	193		T11	8
valid_sources[0x5d]	17416	1			T5	1		T17	2		T30	2
valid_sources[0x5e]	18993	1			T6	1		T10	203		T12	1
valid_sources[0x5f]	17077	1			T3	1		T10	197		T13	495
valid_sources[0x60]	17901	1			T17	1		T30	1		T94	1
valid_sources[0x61]	17622	1			T127	1		T3	1		T10	190
valid_sources[0x62]	17834	1			T6	3		T5	1		T10	206
valid_sources[0x63]	19200	1			T27	1		T2	1990		T30	2
valid_sources[0x64]	16520	1			T17	1		T30	4		T3	3
valid_sources[0x65]	19128	1			T5	5		T127	1		T94	2
valid_sources[0x66]	18829	1			T31	1		T3	2		T10	185
valid_sources[0x67]	18357	1			T22	1		T3	2		T10	186
valid_sources[0x68]	19001	1			T17	3		T30	2		T10	203
valid_sources[0x69]	17608	1			T17	1		T30	1		T3	1
valid_sources[0x6a]	17429	1			T6	1		T42	1		T3	1
valid_sources[0x6b]	18163	1			T17	2		T30	2		T42	1
valid_sources[0x6c]	17432	1			T6	1		T30	3		T31	1
valid_sources[0x6d]	18848	1			T6	1		T5	1		T30	5
valid_sources[0x6e]	16556	1			T30	5		T10	205		T67	4
valid_sources[0x6f]	19794	1			T6	3		T30	1		T10	200
valid_sources[0x70]	17097	1			T27	2		T22	1		T30	7
valid_sources[0x71]	16435	1			T6	1		T27	2		T30	3
valid_sources[0x72]	17804	1			T30	6		T31	1		T3	1
valid_sources[0x73]	18330	1			T102	1		T3	3		T10	181
valid_sources[0x74]	18076	1			T6	1		T5	1		T30	6
valid_sources[0x75]	16577	1			T5	9		T17	1		T19	3
valid_sources[0x76]	17400	1			T3	4		T10	159		T64	1
valid_sources[0x77]	18115	1			T6	1		T18	2		T30	5
valid_sources[0x78]	18781	1			T6	2		T17	1		T10	198
valid_sources[0x79]	17324	1			T22	2		T30	1		T3	1
valid_sources[0x7a]	17257	1			T6	2		T17	2		T23	2
valid_sources[0x7b]	18613	1			T30	2		T31	1		T10	182
valid_sources[0x7c]	17410	1			T6	1		T30	1		T94	1
valid_sources[0x7d]	15670	1			T30	2		T42	1		T31	1
valid_sources[0x7e]	16542	1			T6	1		T19	1		T127	1
valid_sources[0x7f]	17962	1			T30	1		T31	2		T10	188
valid_sources[0x80]	17473	1			T30	2		T42	1		T3	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

968342

1

T4

108

T6

31

T25

33

values[0x0]

all_enables

biggest_size

1469841

1

T4

64

T6

7

T25

8

values[0x1]

all_enables

biggest_size

1418805

1

T4

29

T6

4

T25

3