Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T18
0	1	Covered	T18,T19,T2
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T19
1	0	Covered	T7,T35,T37
1	1	Covered	T4,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1479261723	15386	0	0
GateOpen_A	1479261723	22024	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479261723	15386	0	0
T1	126353	0	0	0
T2	0	58	0	0
T5	293051	0	0	0
T7	3003	19	0	0
T10	0	67	0	0
T17	34436	0	0	0
T18	2915	12	0	0
T19	3341	24	0	0
T20	24334	0	0	0
T25	6401	0	0	0
T26	3261	0	0	0
T27	17344	0	0	0
T35	0	16	0	0
T37	0	1	0	0
T38	0	4	0	0
T39	0	4	0	0
T127	0	28	0	0
T128	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1479261723	22024	0	0
T1	126353	4	0	0
T4	257895	44	0	0
T5	293051	0	0	0
T6	5423	4	0	0
T7	3003	23	0	0
T17	34436	0	0	0
T18	2915	16	0	0
T19	0	28	0	0
T21	0	4	0	0
T22	0	204	0	0
T25	6401	4	0	0
T26	3261	0	0	0
T27	17344	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T18
0	1	Covered	T18,T19,T2
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T19
1	0	Covered	T7,T35,T36
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	163432782	3692	0	0
GateOpen_A	163432782	5351	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432782	3692	0	0
T1	14017	0	0	0
T2	0	15	0	0
T5	32539	0	0	0
T7	324	5	0	0
T10	0	22	0	0
T17	3822	0	0	0
T18	302	3	0	0
T19	358	6	0	0
T20	3058	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2055	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	6	0	0
T128	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432782	5351	0	0
T1	14017	1	0	0
T4	24493	11	0	0
T5	32539	0	0	0
T6	599	1	0	0
T7	324	6	0	0
T17	3822	0	0	0
T18	302	4	0	0
T19	0	7	0	0
T21	0	1	0	0
T22	0	51	0	0
T25	705	1	0	0
T26	354	0	0	0
T27	2055	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T18
0	1	Covered	T18,T19,T2
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T19
1	0	Covered	T7,T35,T36
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	326866581	3884	0	0
GateOpen_A	326866581	5543	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866581	3884	0	0
T1	28033	0	0	0
T2	0	14	0	0
T5	65077	0	0	0
T7	647	5	0	0
T10	0	23	0	0
T17	7644	0	0	0
T18	603	3	0	0
T19	716	6	0	0
T20	6116	0	0	0
T25	1410	0	0	0
T26	708	0	0	0
T27	4109	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	7	0	0
T128	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866581	5543	0	0
T1	28033	1	0	0
T4	48983	11	0	0
T5	65077	0	0	0
T6	1197	1	0	0
T7	647	6	0	0
T17	7644	0	0	0
T18	603	4	0	0
T19	0	7	0	0
T21	0	1	0	0
T22	0	51	0	0
T25	1410	1	0	0
T26	708	0	0	0
T27	4109	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T18
0	1	Covered	T18,T19,T2
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T19
1	0	Covered	T7,T35,T36
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	655127238	3935	0	0
GateOpen_A	655127238	5595	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655127238	3935	0	0
T1	56201	0	0	0
T2	0	15	0	0
T5	130288	0	0	0
T7	1387	5	0	0
T10	0	22	0	0
T17	15313	0	0	0
T18	1340	3	0	0
T19	1511	5	0	0
T20	10106	0	0	0
T25	2857	0	0	0
T26	1466	0	0	0
T27	7453	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	7	0	0
T128	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655127238	5595	0	0
T1	56201	1	0	0
T4	122944	11	0	0
T5	130288	0	0	0
T6	2418	1	0	0
T7	1387	6	0	0
T17	15313	0	0	0
T18	1340	4	0	0
T19	0	6	0	0
T21	0	1	0	0
T22	0	51	0	0
T25	2857	1	0	0
T26	1466	0	0	0
T27	7453	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T18
0	1	Covered	T18,T19,T2
1	0	Covered	T4,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T18,T19
1	0	Covered	T7,T35,T37
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	333835122	3875	0	0
GateOpen_A	333835122	5535	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333835122	3875	0	0
T1	28102	0	0	0
T2	0	14	0	0
T5	65147	0	0	0
T7	645	4	0	0
T17	7657	0	0	0
T18	670	3	0	0
T19	756	7	0	0
T20	5054	0	0	0
T25	1429	0	0	0
T26	733	0	0	0
T27	3727	0	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	8	0	0
T128	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333835122	5535	0	0
T1	28102	1	0	0
T4	61475	11	0	0
T5	65147	0	0	0
T6	1209	1	0	0
T7	645	5	0	0
T17	7657	0	0	0
T18	670	4	0	0
T19	0	8	0	0
T21	0	1	0	0
T22	0	51	0	0
T25	1429	1	0	0
T26	733	0	0	0
T27	3727	1	0	0