Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	867281270	90713	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	867281270	90713	0	0
T1	52685	44	0	0
T2	3051440	1069	0	0
T3	0	242	0	0
T10	0	352	0	0
T11	0	189	0	0
T12	0	118	0	0
T13	0	1952	0	0
T14	0	108	0	0
T15	0	100	0	0
T16	0	495	0	0
T17	19135	0	0	0
T18	6840	0	0	0
T19	7860	0	0	0
T20	12630	0	0	0
T21	6680	0	0	0
T22	64615	0	0	0
T23	10485	0	0	0
T24	5200	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	173456254	13720	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	13720	0	0
T1	10537	7	0	0
T2	610288	141	0	0
T3	0	38	0	0
T10	0	58	0	0
T11	0	30	0	0
T12	0	17	0	0
T13	0	332	0	0
T14	0	15	0	0
T15	0	20	0	0
T16	0	80	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T21	1336	0	0	0
T22	12923	0	0	0
T23	2097	0	0	0
T24	1040	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	173456254	13327	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	13327	0	0
T1	10537	7	0	0
T2	610288	143	0	0
T3	0	36	0	0
T10	0	57	0	0
T11	0	30	0	0
T12	0	17	0	0
T13	0	332	0	0
T14	0	14	0	0
T15	0	20	0	0
T16	0	80	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T21	1336	0	0	0
T22	12923	0	0	0
T23	2097	0	0	0
T24	1040	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	173456254	18261	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	18261	0	0
T1	10537	9	0	0
T2	610288	214	0	0
T3	0	49	0	0
T10	0	71	0	0
T11	0	38	0	0
T12	0	23	0	0
T13	0	393	0	0
T14	0	21	0	0
T15	0	20	0	0
T16	0	100	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T21	1336	0	0	0
T22	12923	0	0	0
T23	2097	0	0	0
T24	1040	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	173456254	18196	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	18196	0	0
T1	10537	9	0	0
T2	610288	214	0	0
T3	0	48	0	0
T10	0	72	0	0
T11	0	39	0	0
T12	0	25	0	0
T13	0	397	0	0
T14	0	21	0	0
T15	0	20	0	0
T16	0	100	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T21	1336	0	0	0
T22	12923	0	0	0
T23	2097	0	0	0
T24	1040	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	173456254	27209	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	27209	0	0
T1	10537	12	0	0
T2	610288	357	0	0
T3	0	71	0	0
T10	0	94	0	0
T11	0	52	0	0
T12	0	36	0	0
T13	0	498	0	0
T14	0	37	0	0
T15	0	20	0	0
T16	0	135	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T21	1336	0	0	0
T22	12923	0	0	0
T23	2097	0	0	0
T24	1040	0	0	0