Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T22,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	173456254	170669435	0	0
AllClkBypReqTrue_A	173456254	152444	0	0
IoClkBypReqFalse_A	173456254	170580364	0	2415
IoClkBypReqTrue_A	173456254	236821	0	0
LcClkBypAckFalse_A	173456254	170678767	0	0
LcClkBypAckTrue_A	173456254	143112	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	170669435	0	0
T1	10537	10488	0	0
T4	6403	3799	0	0
T5	32572	32510	0	0
T6	2367	2288	0	0
T7	1523	1326	0	0
T17	3827	3800	0	0
T18	1368	1131	0	0
T25	2887	2778	0	0
T26	1527	1443	0	0
T27	1862	1828	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	152444	0	0
T2	610288	654	0	0
T10	0	2009	0	0
T20	2526	301	0	0
T21	1336	130	0	0
T22	12923	0	0	0
T23	2097	173	0	0
T24	1040	0	0	0
T30	207431	0	0	0
T35	892	0	0	0
T38	1878	0	0	0
T42	2099	205	0	0
T43	0	80	0	0
T64	0	81	0	0
T102	0	17	0	0
T103	0	255	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	170580364	0	2415
T1	10537	10486	0	3
T4	6403	3777	0	3
T5	32572	32508	0	3
T6	2367	2286	0	3
T7	1523	1324	0	3
T17	3827	3798	0	3
T18	1368	1129	0	3
T25	2887	2776	0	3
T26	1527	1441	0	3
T27	1862	1490	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	236821	0	0
T1	10537	0	0	0
T2	0	1336	0	0
T10	0	2657	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	668	0	0
T21	1336	228	0	0
T22	12923	0	0	0
T23	2097	386	0	0
T24	1040	0	0	0
T27	1862	336	0	0
T42	0	260	0	0
T43	0	234	0	0
T44	0	340	0	0
T103	0	93	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	170678767	0	0
T1	10537	10488	0	0
T4	6403	3799	0	0
T5	32572	32510	0	0
T6	2367	2288	0	0
T7	1523	1326	0	0
T17	3827	3800	0	0
T18	1368	1131	0	0
T25	2887	2778	0	0
T26	1527	1443	0	0
T27	1862	1641	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	143112	0	0
T1	10537	0	0	0
T2	0	836	0	0
T10	0	1488	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	317	0	0
T21	1336	126	0	0
T22	12923	0	0	0
T23	2097	239	0	0
T24	1040	0	0	0
T27	1862	187	0	0
T42	0	124	0	0
T43	0	102	0	0
T44	0	125	0	0
T103	0	85	0	0