Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	15558	0	0
TransStop_A	2147483647	7867	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15558	0	0
T1	234176	0	0	0
T2	0	24	0	0
T5	542880	0	0	0
T6	10072	23	0	0
T7	5252	0	0	0
T10	0	64	0	0
T17	63804	45	0	0
T18	5584	0	0	0
T19	6292	0	0	0
T24	0	10	0	0
T25	11904	37	0	0
T26	6112	0	0	0
T27	31060	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T68	0	4	0	0
T94	0	23	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7867	0	0
T1	234176	0	0	0
T2	0	20	0	0
T5	542880	0	0	0
T6	10072	18	0	0
T7	5252	0	0	0
T10	0	13	0	0
T17	63804	20	0	0
T18	5584	0	0	0
T19	6292	0	0	0
T24	0	7	0	0
T25	11904	15	0	0
T26	6112	0	0	0
T27	31060	0	0	0
T38	0	4	0	0
T39	0	4	0	0
T68	0	4	0	0
T94	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	695303396	3857	0	0
TransStop_A	695303396	1950	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	3857	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	4	0	0
T7	1313	0	0	0
T10	0	15	0	0
T17	15951	10	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	2	0	0
T25	2976	11	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	1950	0	0
T1	58544	0	0	0
T2	0	5	0	0
T5	135720	0	0	0
T6	2518	3	0	0
T7	1313	0	0	0
T10	0	2	0	0
T17	15951	4	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	1	0	0
T25	2976	5	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	695303396	3846	0	0
TransStop_A	695303396	1927	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	3846	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	8	0	0
T7	1313	0	0	0
T10	0	19	0	0
T17	15951	11	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	4	0	0
T25	2976	10	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	1927	0	0
T1	58544	0	0	0
T2	0	5	0	0
T5	135720	0	0	0
T6	2518	7	0	0
T7	1313	0	0	0
T10	0	5	0	0
T17	15951	6	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	2	0	0
T25	2976	3	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	695303396	3931	0	0
TransStop_A	695303396	2019	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	3931	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	6	0	0
T7	1313	0	0	0
T10	0	16	0	0
T17	15951	14	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	2	0	0
T25	2976	10	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	2019	0	0
T1	58544	0	0	0
T2	0	5	0	0
T5	135720	0	0	0
T6	2518	5	0	0
T7	1313	0	0	0
T10	0	4	0	0
T17	15951	7	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	2	0	0
T25	2976	4	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	695303396	3924	0	0
TransStop_A	695303396	1971	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	3924	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	5	0	0
T7	1313	0	0	0
T10	0	14	0	0
T17	15951	10	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	2	0	0
T25	2976	6	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695303396	1971	0	0
T1	58544	0	0	0
T2	0	5	0	0
T5	135720	0	0	0
T6	2518	3	0	0
T7	1313	0	0	0
T10	0	2	0	0
T17	15951	3	0	0
T18	1396	0	0	0
T19	1573	0	0	0
T24	0	2	0	0
T25	2976	3	0	0
T26	1528	0	0	0
T27	7765	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T68	0	1	0	0
T94	0	1	0	0