Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	173456254	25323488	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	25323488	0	58
T1	10537	2779	0	1
T2	0	121773	0	0
T3	0	21025	0	1
T5	32572	835	0	1
T10	0	24871	0	0
T11	0	13102	0	1
T12	0	10395	0	1
T13	0	781282	0	0
T14	0	12902	0	1
T15	0	2551	0	1
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T21	1336	0	0	0
T22	12923	0	0	0
T26	1527	0	0	0
T27	1862	0	0	0
T104	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1