Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	174377717	5624469	0	0
clk_enables_rd_A	174377717	62147	0	0
clk_hints_rd_A	174377717	56007	0	0
extclk_ctrl_rd_A	174377717	69078	0	0
extclk_ctrl_regwen_rd_A	174377717	54361	0	0
jitter_enable_rd_A	174377717	76474	0	0
jitter_regwen_rd_A	174377717	59297	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174377717	5624469	0	0
T10	224072	71909	0	0
T11	29891	0	0	0
T13	0	143951	0	0
T29	0	142526	0	0
T57	0	120907	0	0
T58	0	134851	0	0
T59	0	118909	0	0
T60	0	51025	0	0
T61	0	137994	0	0
T62	0	142515	0	0
T63	0	49412	0	0
T64	1280	0	0	0
T65	1439	0	0	0
T66	1343	0	0	0
T67	2063	0	0	0
T68	1347	0	0	0
T69	2084	0	0	0
T70	1595	0	0	0
T71	1551	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174377717	62147	0	0
T10	0	1208	0	0
T29	0	2672	0	0
T30	207431	0	0	0
T31	47067	0	0	0
T35	892	0	0	0
T38	1878	5	0	0
T42	2099	0	0	0
T43	1185	0	0	0
T44	2113	0	0	0
T61	0	5630	0	0
T63	0	1793	0	0
T94	2541	0	0	0
T122	0	3	0	0
T123	0	2733	0	0
T124	0	2711	0	0
T125	0	4816	0	0
T126	0	861	0	0
T127	1711	0	0	0
T128	808	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174377717	56007	0	0
T10	0	1289	0	0
T29	0	2921	0	0
T30	207431	0	0	0
T31	47067	0	0	0
T35	892	0	0	0
T38	1878	3	0	0
T42	2099	0	0	0
T43	1185	0	0	0
T44	2113	0	0	0
T61	0	5367	0	0
T63	0	1698	0	0
T94	2541	0	0	0
T122	0	3	0	0
T123	0	2513	0	0
T124	0	2686	0	0
T127	1711	0	0	0
T128	808	0	0	0
T129	0	9	0	0
T130	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174377717	69078	0	0
T2	610288	0	0	0
T10	0	1475	0	0
T20	2526	59	0	0
T21	1336	0	0	0
T22	12923	0	0	0
T23	2097	0	0	0
T24	1040	0	0	0
T29	0	3607	0	0
T30	207431	0	0	0
T35	892	0	0	0
T38	1878	0	0	0
T42	2099	0	0	0
T61	0	5955	0	0
T73	0	21	0	0
T103	0	50	0	0
T131	0	17	0	0
T132	0	47	0	0
T133	0	6	0	0
T134	0	7	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174377717	54361	0	0
T10	224072	1217	0	0
T11	29891	0	0	0
T29	0	2395	0	0
T61	0	4795	0	0
T63	0	1724	0	0
T64	1280	0	0	0
T65	1439	0	0	0
T66	1343	0	0	0
T67	2063	0	0	0
T68	1347	0	0	0
T69	2084	0	0	0
T70	1595	0	0	0
T71	1551	0	0	0
T123	0	2355	0	0
T124	0	2840	0	0
T125	0	4118	0	0
T135	0	61	0	0
T136	0	47	0	0
T137	0	30	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174377717	76474	0	0
T10	0	1843	0	0
T29	0	3084	0	0
T30	207431	0	0	0
T31	47067	0	0	0
T35	892	0	0	0
T38	1878	98	0	0
T42	2099	0	0	0
T43	1185	0	0	0
T44	2113	0	0	0
T61	0	6137	0	0
T63	0	2252	0	0
T94	2541	0	0	0
T122	0	108	0	0
T123	0	2991	0	0
T127	1711	0	0	0
T128	808	0	0	0
T129	0	30	0	0
T130	0	58	0	0
T138	0	63	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	174377717	59297	0	0
T10	224072	1374	0	0
T11	29891	0	0	0
T29	0	2607	0	0
T61	0	5547	0	0
T63	0	1887	0	0
T64	1280	0	0	0
T65	1439	0	0	0
T66	1343	0	0	0
T67	2063	0	0	0
T68	1347	0	0	0
T69	2084	0	0	0
T70	1595	0	0	0
T71	1551	0	0	0
T123	0	2345	0	0
T124	0	3026	0	0
T125	0	4538	0	0
T126	0	789	0	0
T139	0	4245	0	0
T140	0	3798	0	0