Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T5
1	0	Covered	T20,T21,T23
1	1	Covered	T27,T20,T21

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	655127238	5108	0	0
g_div2.Div2Whole_A	655127238	5818	0	0
g_div4.Div4Stepped_A	326866581	5029	0	0
g_div4.Div4Whole_A	326866581	5603	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655127238	5108	0	0
T1	56201	0	0	0
T2	0	26	0	0
T17	15313	0	0	0
T18	1340	0	0	0
T19	1511	0	0	0
T20	10106	11	0	0
T21	6417	3	0	0
T22	68925	0	0	0
T23	8390	11	0	0
T24	3997	0	0	0
T27	7453	10	0	0
T42	0	5	0	0
T43	0	5	0	0
T44	0	6	0	0
T102	0	3	0	0
T103	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655127238	5818	0	0
T1	56201	0	0	0
T2	0	35	0	0
T17	15313	0	0	0
T18	1340	0	0	0
T19	1511	0	0	0
T20	10106	13	0	0
T21	6417	3	0	0
T22	68925	0	0	0
T23	8390	11	0	0
T24	3997	0	0	0
T27	7453	12	0	0
T42	0	9	0	0
T43	0	5	0	0
T44	0	9	0	0
T102	0	3	0	0
T103	0	12	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866581	5029	0	0
T1	28033	0	0	0
T2	0	25	0	0
T17	7644	0	0	0
T18	603	0	0	0
T19	716	0	0	0
T20	6116	11	0	0
T21	3509	3	0	0
T22	32237	0	0	0
T23	4758	11	0	0
T24	1973	0	0	0
T27	4109	10	0	0
T42	0	4	0	0
T43	0	5	0	0
T44	0	6	0	0
T102	0	2	0	0
T103	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866581	5603	0	0
T1	28033	0	0	0
T2	0	31	0	0
T17	7644	0	0	0
T18	603	0	0	0
T19	716	0	0	0
T20	6116	13	0	0
T21	3509	3	0	0
T22	32237	0	0	0
T23	4758	11	0	0
T24	1973	0	0	0
T27	4109	12	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	9	0	0
T102	0	3	0	0
T103	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T5
1	0	Covered	T20,T21,T23
1	1	Covered	T27,T20,T21

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	655127238	5108	0	0
g_div2.Div2Whole_A	655127238	5818	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655127238	5108	0	0
T1	56201	0	0	0
T2	0	26	0	0
T17	15313	0	0	0
T18	1340	0	0	0
T19	1511	0	0	0
T20	10106	11	0	0
T21	6417	3	0	0
T22	68925	0	0	0
T23	8390	11	0	0
T24	3997	0	0	0
T27	7453	10	0	0
T42	0	5	0	0
T43	0	5	0	0
T44	0	6	0	0
T102	0	3	0	0
T103	0	6	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655127238	5818	0	0
T1	56201	0	0	0
T2	0	35	0	0
T17	15313	0	0	0
T18	1340	0	0	0
T19	1511	0	0	0
T20	10106	13	0	0
T21	6417	3	0	0
T22	68925	0	0	0
T23	8390	11	0	0
T24	3997	0	0	0
T27	7453	12	0	0
T42	0	9	0	0
T43	0	5	0	0
T44	0	9	0	0
T102	0	3	0	0
T103	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T25,T5
1	0	Covered	T20,T21,T23
1	1	Covered	T27,T20,T21

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	326866581	5029	0	0
g_div4.Div4Whole_A	326866581	5603	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866581	5029	0	0
T1	28033	0	0	0
T2	0	25	0	0
T17	7644	0	0	0
T18	603	0	0	0
T19	716	0	0	0
T20	6116	11	0	0
T21	3509	3	0	0
T22	32237	0	0	0
T23	4758	11	0	0
T24	1973	0	0	0
T27	4109	10	0	0
T42	0	4	0	0
T43	0	5	0	0
T44	0	6	0	0
T102	0	2	0	0
T103	0	6	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866581	5603	0	0
T1	28033	0	0	0
T2	0	31	0	0
T17	7644	0	0	0
T18	603	0	0	0
T19	716	0	0	0
T20	6116	13	0	0
T21	3509	3	0	0
T22	32237	0	0	0
T23	4758	11	0	0
T24	1973	0	0	0
T27	4109	12	0	0
T42	0	8	0	0
T43	0	5	0	0
T44	0	9	0	0
T102	0	3	0	0
T103	0	10	0	0