Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	520368762	451	0	0
StatusRise_A	520368762	451	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520368762	451	0	0
T1	31611	0	0	0
T5	97716	0	0	0
T7	4569	14	0	0
T17	11481	0	0	0
T18	4104	0	0	0
T19	4716	0	0	0
T20	7578	0	0	0
T25	8661	0	0	0
T26	4581	0	0	0
T27	5586	0	0	0
T35	0	11	0	0
T36	0	3	0	0
T37	0	2	0	0
T141	0	11	0	0
T142	0	1	0	0
T143	0	10	0	0
T144	0	12	0	0
T145	0	15	0	0
T146	0	9	0	0
T147	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	520368762	451	0	0
T1	31611	0	0	0
T5	97716	0	0	0
T7	4569	14	0	0
T17	11481	0	0	0
T18	4104	0	0	0
T19	4716	0	0	0
T20	7578	0	0	0
T25	8661	0	0	0
T26	4581	0	0	0
T27	5586	0	0	0
T35	0	11	0	0
T36	0	3	0	0
T37	0	2	0	0
T141	0	11	0	0
T142	0	1	0	0
T143	0	10	0	0
T144	0	12	0	0
T145	0	15	0	0
T146	0	9	0	0
T147	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	173456254	154	0	0
StatusRise_A	173456254	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	154	0	0
T1	10537	0	0	0
T5	32572	0	0	0
T7	1523	5	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T25	2887	0	0	0
T26	1527	0	0	0
T27	1862	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	4	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	5	0	0
T146	0	4	0	0
T147	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	154	0	0
T1	10537	0	0	0
T5	32572	0	0	0
T7	1523	5	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T25	2887	0	0	0
T26	1527	0	0	0
T27	1862	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	4	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	5	0	0
T146	0	4	0	0
T147	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	173456254	155	0	0
StatusRise_A	173456254	155	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	155	0	0
T1	10537	0	0	0
T5	32572	0	0	0
T7	1523	5	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T25	2887	0	0	0
T26	1527	0	0	0
T27	1862	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0
T146	0	3	0	0
T147	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	155	0	0
T1	10537	0	0	0
T5	32572	0	0	0
T7	1523	5	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T25	2887	0	0	0
T26	1527	0	0	0
T27	1862	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0
T146	0	3	0	0
T147	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	173456254	142	0	0
StatusRise_A	173456254	142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	142	0	0
T1	10537	0	0	0
T5	32572	0	0	0
T7	1523	4	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T25	2887	0	0	0
T26	1527	0	0	0
T27	1862	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173456254	142	0	0
T1	10537	0	0	0
T5	32572	0	0	0
T7	1523	4	0	0
T17	3827	0	0	0
T18	1368	0	0	0
T19	1572	0	0	0
T20	2526	0	0	0
T25	2887	0	0	0
T26	1527	0	0	0
T27	1862	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0