Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50727	0	0
CgEnOn_A	2147483647	41329	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50727	0	0
T1	631996	3	0	0
T2	0	6	0	0
T4	257893	33	0	0
T5	1465492	3	0	0
T6	15491	7	0	0
T7	14522	48	0	0
T17	172218	13	0	0
T18	14796	20	0	0
T19	13486	0	0	0
T20	51499	0	0	0
T24	0	2	0	0
T25	32064	14	0	0
T26	16388	3	0	0
T27	85374	3	0	0
T29	0	5	0	0
T35	0	23	0	0
T36	0	5	0	0
T62	0	5	0	0
T141	0	20	0	0
T142	0	5	0	0
T143	0	20	0	0
T144	0	15	0	0
T145	0	30	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41329	0	0
T1	631996	0	0	0
T2	0	73	0	0
T5	1465492	0	0	0
T6	10072	4	0	0
T7	14522	45	0	0
T10	0	131	0	0
T17	172218	0	0	0
T18	14796	17	0	0
T19	16824	18	0	0
T20	75830	0	0	0
T25	32064	0	0	0
T26	16388	0	0	0
T27	85374	0	0	0
T29	0	4	0	0
T35	0	35	0	0
T36	0	5	0	0
T38	0	4	0	0
T39	0	3	0	0
T62	0	4	0	0
T124	0	1	0	0
T127	0	33	0	0
T128	0	10	0	0
T141	0	20	0	0
T142	0	5	0	0
T143	0	20	0	0
T144	0	15	0	0
T145	0	30	0	0
T146	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	326866167	158	0	0
CgEnOn_A	326866167	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866167	158	0	0
T1	28033	0	0	0
T5	65076	0	0	0
T7	646	5	0	0
T17	7644	0	0	0
T18	602	0	0	0
T19	715	0	0	0
T20	6115	0	0	0
T25	1409	0	0	0
T26	707	0	0	0
T27	4108	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866167	158	0	0
T1	28033	0	0	0
T5	65076	0	0	0
T7	646	5	0	0
T17	7644	0	0	0
T18	602	0	0	0
T19	715	0	0	0
T20	6115	0	0	0
T25	1409	0	0	0
T26	707	0	0	0
T27	4108	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	163432382	158	0	0
CgEnOn_A	163432382	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	158	0	0
T1	14016	0	0	0
T5	32538	0	0	0
T7	323	5	0	0
T17	3822	0	0	0
T18	301	0	0	0
T19	358	0	0	0
T20	3057	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2054	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	158	0	0
T1	14016	0	0	0
T5	32538	0	0	0
T7	323	5	0	0
T17	3822	0	0	0
T18	301	0	0	0
T19	358	0	0	0
T20	3057	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2054	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	163432382	158	0	0
CgEnOn_A	163432382	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	158	0	0
T1	14016	0	0	0
T5	32538	0	0	0
T7	323	5	0	0
T17	3822	0	0	0
T18	301	0	0	0
T19	358	0	0	0
T20	3057	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2054	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	158	0	0
T1	14016	0	0	0
T5	32538	0	0	0
T7	323	5	0	0
T17	3822	0	0	0
T18	301	0	0	0
T19	358	0	0	0
T20	3057	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2054	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	163432382	158	0	0
CgEnOn_A	163432382	158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	158	0	0
T1	14016	0	0	0
T5	32538	0	0	0
T7	323	5	0	0
T17	3822	0	0	0
T18	301	0	0	0
T19	358	0	0	0
T20	3057	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2054	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	158	0	0
T1	14016	0	0	0
T5	32538	0	0	0
T7	323	5	0	0
T17	3822	0	0	0
T18	301	0	0	0
T19	358	0	0	0
T20	3057	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2054	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	655126800	158	0	0
CgEnOn_A	655126800	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655126800	158	0	0
T1	56200	0	0	0
T5	130287	0	0	0
T7	1386	5	0	0
T17	15312	0	0	0
T18	1339	0	0	0
T19	1510	0	0	0
T20	10106	0	0	0
T25	2857	0	0	0
T26	1466	0	0	0
T27	7453	0	0	0
T29	0	1	0	0
T35	0	4	0	0
T36	0	1	0	0
T62	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655126800	156	0	0
T1	56200	0	0	0
T5	130287	0	0	0
T7	1386	5	0	0
T17	15312	0	0	0
T18	1339	0	0	0
T19	1510	0	0	0
T20	10106	0	0	0
T25	2857	0	0	0
T26	1466	0	0	0
T27	7453	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T124	0	1	0	0
T141	0	4	0	0
T142	0	1	0	0
T143	0	4	0	0
T144	0	3	0	0
T145	0	6	0	0
T146	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	695302957	156	0	0
CgEnOn_A	695302957	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	156	0	0
T1	58544	0	0	0
T5	135720	0	0	0
T7	1313	5	0	0
T17	15951	0	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T20	10527	0	0	0
T25	2976	0	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	4	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	5	0	0
T146	0	4	0	0
T147	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	154	0	0
T1	58544	0	0	0
T5	135720	0	0	0
T7	1313	5	0	0
T17	15951	0	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T20	10527	0	0	0
T25	2976	0	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	4	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	5	0	0
T146	0	4	0	0
T147	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	695302957	156	0	0
CgEnOn_A	695302957	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	156	0	0
T1	58544	0	0	0
T5	135720	0	0	0
T7	1313	5	0	0
T17	15951	0	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T20	10527	0	0	0
T25	2976	0	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	4	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	5	0	0
T146	0	4	0	0
T147	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	154	0	0
T1	58544	0	0	0
T5	135720	0	0	0
T7	1313	5	0	0
T17	15951	0	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T20	10527	0	0	0
T25	2976	0	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	4	0	0
T143	0	4	0	0
T144	0	4	0	0
T145	0	5	0	0
T146	0	4	0	0
T147	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	333834714	145	0	0
CgEnOn_A	333834714	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333834714	145	0	0
T1	28101	0	0	0
T5	65147	0	0	0
T7	644	4	0	0
T13	0	1	0	0
T17	7656	0	0	0
T18	670	0	0	0
T19	755	0	0	0
T20	5053	0	0	0
T25	1428	0	0	0
T26	732	0	0	0
T27	3726	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	4	0	0
T146	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333834714	142	0	0
T1	28101	0	0	0
T5	65147	0	0	0
T7	644	4	0	0
T17	7656	0	0	0
T18	670	0	0	0
T19	755	0	0	0
T20	5053	0	0	0
T25	1428	0	0	0
T26	732	0	0	0
T27	3726	0	0	0
T35	0	4	0	0
T36	0	1	0	0
T37	0	1	0	0
T141	0	3	0	0
T143	0	2	0	0
T144	0	5	0	0
T145	0	4	0	0
T146	0	2	0	0
T147	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T35,T36
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	163432382	8308	0	0
CgEnOn_A	163432382	5964	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	8308	0	0
T1	14016	1	0	0
T4	24493	11	0	0
T5	32538	1	0	0
T6	598	1	0	0
T7	323	6	0	0
T17	3822	1	0	0
T18	301	6	0	0
T25	705	1	0	0
T26	354	1	0	0
T27	2054	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163432382	5964	0	0
T1	14016	0	0	0
T2	0	22	0	0
T5	32538	0	0	0
T7	323	5	0	0
T10	0	44	0	0
T17	3822	0	0	0
T18	301	5	0	0
T19	358	6	0	0
T20	3057	0	0	0
T25	705	0	0	0
T26	354	0	0	0
T27	2054	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	10	0	0
T128	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T35,T36
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	326866167	8322	0	0
CgEnOn_A	326866167	5978	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866167	8322	0	0
T1	28033	1	0	0
T4	48983	11	0	0
T5	65076	1	0	0
T6	1196	1	0	0
T7	646	6	0	0
T17	7644	1	0	0
T18	602	7	0	0
T25	1409	1	0	0
T26	707	1	0	0
T27	4108	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326866167	5978	0	0
T1	28033	0	0	0
T2	0	22	0	0
T5	65076	0	0	0
T7	646	5	0	0
T10	0	42	0	0
T17	7644	0	0	0
T18	602	6	0	0
T19	715	7	0	0
T20	6115	0	0	0
T25	1409	0	0	0
T26	707	0	0	0
T27	4108	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	12	0	0
T128	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T35,T36
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	655126800	8358	0	0
CgEnOn_A	655126800	6012	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655126800	8358	0	0
T1	56200	1	0	0
T4	122943	11	0	0
T5	130287	1	0	0
T6	2417	1	0	0
T7	1386	6	0	0
T17	15312	1	0	0
T18	1339	7	0	0
T25	2857	1	0	0
T26	1466	1	0	0
T27	7453	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	655126800	6012	0	0
T1	56200	0	0	0
T2	0	23	0	0
T5	130287	0	0	0
T7	1386	5	0	0
T10	0	45	0	0
T17	15312	0	0	0
T18	1339	6	0	0
T19	1510	5	0	0
T20	10106	0	0	0
T25	2857	0	0	0
T26	1466	0	0	0
T27	7453	0	0	0
T35	0	4	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	11	0	0
T128	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T35,T37
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	333834714	8310	0	0
CgEnOn_A	333834714	5963	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333834714	8310	0	0
T1	28101	1	0	0
T4	61474	11	0	0
T5	65147	1	0	0
T6	1208	1	0	0
T7	644	5	0	0
T17	7656	1	0	0
T18	670	8	0	0
T25	1428	1	0	0
T26	732	1	0	0
T27	3726	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	333834714	5963	0	0
T1	28101	0	0	0
T2	0	23	0	0
T5	65147	0	0	0
T7	644	4	0	0
T17	7656	0	0	0
T18	670	7	0	0
T19	755	7	0	0
T20	5053	0	0	0
T25	1428	0	0	0
T26	732	0	0	0
T27	3726	0	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T127	0	11	0	0
T128	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Covered	T6,T25,T17
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	695302957	4013	0	0
CgEnOn_A	695302957	4011	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4013	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	4	0	0
T7	1313	5	0	0
T17	15951	10	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	2	0	0
T25	2976	11	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4011	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	4	0	0
T7	1313	5	0	0
T17	15951	10	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	2	0	0
T25	2976	11	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Covered	T6,T25,T17
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	695302957	4002	0	0
CgEnOn_A	695302957	4000	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4002	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	8	0	0
T7	1313	5	0	0
T17	15951	11	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	4	0	0
T25	2976	10	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4000	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	8	0	0
T7	1313	5	0	0
T17	15951	11	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	4	0	0
T25	2976	10	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Covered	T6,T25,T17
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	695302957	4087	0	0
CgEnOn_A	695302957	4085	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4087	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	6	0	0
T7	1313	5	0	0
T17	15951	14	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	2	0	0
T25	2976	10	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4085	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	6	0	0
T7	1313	5	0	0
T17	15951	14	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	2	0	0
T25	2976	10	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T22
1	0	Covered	T6,T25,T17
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	695302957	4080	0	0
CgEnOn_A	695302957	4078	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4080	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	5	0	0
T7	1313	5	0	0
T17	15951	10	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	2	0	0
T25	2976	6	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	695302957	4078	0	0
T1	58544	0	0	0
T2	0	6	0	0
T5	135720	0	0	0
T6	2518	5	0	0
T7	1313	5	0	0
T17	15951	10	0	0
T18	1395	0	0	0
T19	1572	0	0	0
T24	0	2	0	0
T25	2976	6	0	0
T26	1527	0	0	0
T27	7764	0	0	0
T35	0	3	0	0
T37	0	1	0	0
T38	0	1	0	0
T94	0	5	0	0