Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	586613	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3466922

1

T7

66

T8

6

T5

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	998922	1			T7	80		T8	5		T5	6
values[0x0]	1403177	1			T7	28		T8	6		T5	66
values[0x1]	1651436	1			T7	32		T8	5		T5	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	320183	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3733352

1

T7

78

T8

7

T5

88

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15164	1			T1	298		T24	2		T3	8
valid_sources[0x01]	16872	1			T1	319		T2	4		T3	2
valid_sources[0x02]	15549	1			T1	313		T24	2		T2	1
valid_sources[0x03]	15924	1			T7	2		T1	314		T2	1
valid_sources[0x04]	15894	1			T1	336		T2	7		T29	2
valid_sources[0x05]	15972	1			T5	6		T1	316		T19	1
valid_sources[0x06]	16337	1			T1	295		T2	1		T117	1
valid_sources[0x07]	16052	1			T1	326		T2	1		T29	3
valid_sources[0x08]	16149	1			T7	1		T1	297		T19	2
valid_sources[0x09]	16218	1			T1	301		T25	1		T3	7
valid_sources[0x0a]	14949	1			T1	264		T2	2		T29	2
valid_sources[0x0b]	17249	1			T1	316		T30	1		T189	1
valid_sources[0x0c]	14674	1			T1	336		T2	1		T30	5
valid_sources[0x0d]	15566	1			T8	1		T1	280		T22	1
valid_sources[0x0e]	15235	1			T7	1		T1	340		T25	1
valid_sources[0x0f]	15176	1			T1	265		T2	6		T29	3
valid_sources[0x10]	14856	1			T7	1		T1	314		T29	5
valid_sources[0x11]	18667	1			T1	325		T22	2		T25	1
valid_sources[0x12]	17568	1			T7	1		T8	1		T5	5
valid_sources[0x13]	15878	1			T1	273		T24	1		T25	1
valid_sources[0x14]	15975	1			T5	3		T1	291		T124	1
valid_sources[0x15]	15876	1			T1	322		T19	2		T29	5
valid_sources[0x16]	15731	1			T1	304		T22	2		T2	4
valid_sources[0x17]	14913	1			T7	2		T5	15		T1	285
valid_sources[0x18]	16428	1			T1	288		T19	1		T2	7
valid_sources[0x19]	15140	1			T7	4		T1	316		T29	3
valid_sources[0x1a]	16589	1			T7	1		T1	319		T22	5
valid_sources[0x1b]	16117	1			T7	1		T1	329		T3	3
valid_sources[0x1c]	15552	1			T7	1		T1	300		T29	8
valid_sources[0x1d]	15935	1			T1	273		T22	4		T2	2
valid_sources[0x1e]	17411	1			T1	285		T19	2		T6	3
valid_sources[0x1f]	15702	1			T1	303		T19	1		T22	4
valid_sources[0x20]	17363	1			T1	331		T6	35		T22	2
valid_sources[0x21]	16857	1			T7	1		T1	278		T23	1
valid_sources[0x22]	15979	1			T5	7		T1	306		T2	6
valid_sources[0x23]	16932	1			T1	304		T25	1		T42	81
valid_sources[0x24]	15852	1			T1	312		T32	1		T29	2
valid_sources[0x25]	15906	1			T1	319		T19	1		T2	1
valid_sources[0x26]	16275	1			T5	2		T1	319		T2	2
valid_sources[0x27]	16052	1			T7	2		T1	296		T3	2
valid_sources[0x28]	14617	1			T1	316		T24	1		T25	1
valid_sources[0x29]	16073	1			T1	301		T2	2		T30	3
valid_sources[0x2a]	15528	1			T5	9		T1	288		T22	2
valid_sources[0x2b]	16097	1			T1	324		T23	1		T3	3
valid_sources[0x2c]	15709	1			T7	2		T1	300		T29	4
valid_sources[0x2d]	15144	1			T1	309		T3	12		T29	7
valid_sources[0x2e]	14708	1			T7	3		T1	290		T29	4
valid_sources[0x2f]	15790	1			T1	312		T19	1		T23	1
valid_sources[0x30]	15352	1			T1	298		T21	6		T2	2
valid_sources[0x31]	15284	1			T1	312		T19	1		T22	3
valid_sources[0x32]	15075	1			T1	303		T3	1		T29	3
valid_sources[0x33]	15849	1			T1	285		T22	1		T32	1
valid_sources[0x34]	15720	1			T1	323		T19	1		T24	1
valid_sources[0x35]	14966	1			T7	3		T1	303		T6	42
valid_sources[0x36]	14846	1			T1	314		T2	2		T3	1
valid_sources[0x37]	15259	1			T1	299		T22	1		T29	1
valid_sources[0x38]	16333	1			T1	308		T29	2		T30	1
valid_sources[0x39]	15666	1			T7	2		T1	318		T25	1
valid_sources[0x3a]	14603	1			T1	335		T22	1		T11	1
valid_sources[0x3b]	16557	1			T7	1		T1	299		T2	1
valid_sources[0x3c]	15623	1			T7	3		T1	312		T24	1
valid_sources[0x3d]	15306	1			T1	331		T2	2		T3	28
valid_sources[0x3e]	16833	1			T1	278		T2	1		T29	1
valid_sources[0x3f]	15826	1			T1	286		T25	1		T2	4
valid_sources[0x40]	15420	1			T8	2		T1	298		T2	2
valid_sources[0x41]	16596	1			T1	303		T2	1		T29	2
valid_sources[0x42]	16512	1			T1	253		T6	32		T23	1
valid_sources[0x43]	15492	1			T7	2		T1	299		T19	1
valid_sources[0x44]	15455	1			T1	343		T29	1		T30	1
valid_sources[0x45]	15627	1			T7	1		T1	309		T2	15
valid_sources[0x46]	15209	1			T7	1		T1	283		T19	1
valid_sources[0x47]	14855	1			T1	314		T19	2		T21	1
valid_sources[0x48]	15391	1			T5	14		T1	269		T29	4
valid_sources[0x49]	14987	1			T5	10		T1	271		T6	11
valid_sources[0x4a]	15196	1			T1	354		T2	1		T29	3
valid_sources[0x4b]	16213	1			T1	311		T24	3		T2	4
valid_sources[0x4c]	15229	1			T1	276		T22	1		T2	4
valid_sources[0x4d]	15511	1			T1	278		T23	1		T24	1
valid_sources[0x4e]	16049	1			T7	7		T1	339		T25	2
valid_sources[0x4f]	16807	1			T5	3		T1	285		T25	1
valid_sources[0x50]	16265	1			T7	2		T1	293		T19	1
valid_sources[0x51]	16511	1			T1	278		T29	1		T30	1
valid_sources[0x52]	16443	1			T1	308		T19	1		T22	1
valid_sources[0x53]	16706	1			T1	326		T22	4		T29	5
valid_sources[0x54]	15177	1			T1	306		T24	1		T25	1
valid_sources[0x55]	15913	1			T1	279		T29	5		T104	1
valid_sources[0x56]	16507	1			T7	1		T1	267		T29	8
valid_sources[0x57]	15107	1			T1	282		T22	1		T25	1
valid_sources[0x58]	15983	1			T7	1		T1	311		T19	1
valid_sources[0x59]	15905	1			T1	290		T29	1		T30	4
valid_sources[0x5a]	16762	1			T1	323		T24	1		T29	3
valid_sources[0x5b]	15019	1			T1	301		T19	2		T22	1
valid_sources[0x5c]	15805	1			T1	335		T24	1		T25	1
valid_sources[0x5d]	15065	1			T1	319		T23	1		T2	2
valid_sources[0x5e]	15518	1			T5	3		T1	266		T6	1
valid_sources[0x5f]	19772	1			T1	313		T4	658		T3	2
valid_sources[0x60]	14642	1			T1	303		T25	1		T2	1
valid_sources[0x61]	15928	1			T7	2		T1	345		T29	1
valid_sources[0x62]	15907	1			T1	279		T2	2		T29	5
valid_sources[0x63]	17253	1			T8	1		T1	301		T24	2
valid_sources[0x64]	16926	1			T1	281		T23	1		T29	1
valid_sources[0x65]	15847	1			T7	1		T1	299		T2	3
valid_sources[0x66]	15822	1			T1	281		T2	1		T32	1
valid_sources[0x67]	15170	1			T1	305		T22	2		T2	3
valid_sources[0x68]	14712	1			T7	1		T1	315		T23	1
valid_sources[0x69]	15532	1			T1	308		T29	4		T11	1
valid_sources[0x6a]	16286	1			T7	1		T1	337		T19	1
valid_sources[0x6b]	14146	1			T1	297		T6	18		T25	1
valid_sources[0x6c]	15370	1			T7	1		T1	280		T2	1
valid_sources[0x6d]	15909	1			T7	1		T1	321		T32	1
valid_sources[0x6e]	15403	1			T7	1		T1	336		T23	1
valid_sources[0x6f]	15163	1			T1	300		T2	2		T3	1
valid_sources[0x70]	15725	1			T1	265		T19	1		T3	2
valid_sources[0x71]	14890	1			T1	306		T19	3		T2	3
valid_sources[0x72]	15412	1			T8	1		T26	63		T1	266
valid_sources[0x73]	15702	1			T1	300		T19	1		T2	2
valid_sources[0x74]	14659	1			T7	1		T1	335		T29	2
valid_sources[0x75]	16729	1			T8	1		T1	284		T22	4
valid_sources[0x76]	14336	1			T7	1		T1	290		T24	1
valid_sources[0x77]	15727	1			T7	2		T1	306		T25	2
valid_sources[0x78]	15568	1			T7	1		T1	246		T19	1
valid_sources[0x79]	15538	1			T7	1		T1	280		T32	1
valid_sources[0x7a]	15006	1			T7	11		T1	290		T23	1
valid_sources[0x7b]	16093	1			T1	317		T2	5		T32	2
valid_sources[0x7c]	15703	1			T1	342		T3	9		T29	10
valid_sources[0x7d]	15681	1			T1	309		T25	1		T3	11
valid_sources[0x7e]	14799	1			T7	5		T1	268		T29	6
valid_sources[0x7f]	16411	1			T7	1		T1	298		T23	1
valid_sources[0x80]	16167	1			T1	301		T24	1		T29	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

875896

1

T7

41

T8

2

T5

1

values[0x0]

all_enables

biggest_size

1316689

1

T7

14

T8

3

T5

42

values[0x1]

all_enables

biggest_size

1274337

1

T7

11

T8

1

T5

24