Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T22
0	1	Covered	T1,T123,T157
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T22
1	0	Covered	T38,T39,T40
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	971076633	12988	0	0
GateOpen_A	971076633	19805	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971076633	12988	0	0
T1	1710507	276	0	0
T6	219787	0	0	0
T12	0	4	0	0
T18	10647	0	0	0
T19	114442	0	0	0
T20	4684	0	0	0
T21	6348	0	0	0
T22	3501	4	0	0
T23	4455	0	0	0
T24	4972	0	0	0
T25	6075	0	0	0
T38	0	20	0	0
T39	0	3	0	0
T40	0	5	0	0
T42	0	4	0	0
T122	0	3	0	0
T123	0	8	0	0
T157	0	9	0	0
T190	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	971076633	19805	0	0
T1	1710507	292	0	0
T2	0	4	0	0
T6	219787	4	0	0
T18	10647	4	0	0
T19	114442	204	0	0
T20	4684	0	0	0
T21	6348	4	0	0
T22	3501	8	0	0
T23	4455	4	0	0
T24	4972	0	0	0
T25	0	4	0	0
T26	8881	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T22
0	1	Covered	T1,T123,T157
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T22
1	0	Covered	T38,T39,T40
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	107116763	3074	0	0
GateOpen_A	107116763	4778	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116763	3074	0	0
T1	189684	69	0	0
T6	22163	0	0	0
T12	0	1	0	0
T18	1163	0	0	0
T19	12079	0	0	0
T20	543	0	0	0
T21	741	0	0	0
T22	383	1	0	0
T23	475	0	0	0
T24	574	0	0	0
T25	727	0	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T42	0	1	0	0
T123	0	2	0	0
T157	0	2	0	0
T190	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116763	4778	0	0
T1	189684	73	0	0
T2	0	1	0	0
T6	22163	1	0	0
T18	1163	1	0	0
T19	12079	51	0	0
T20	543	0	0	0
T21	741	1	0	0
T22	383	2	0	0
T23	475	1	0	0
T24	574	0	0	0
T25	0	1	0	0
T26	974	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T22
0	1	Covered	T1,T123,T157
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T22
1	0	Covered	T38,T39,T40
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	214234324	3319	0	0
GateOpen_A	214234324	5023	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214234324	3319	0	0
T1	379369	67	0	0
T6	44325	0	0	0
T12	0	1	0	0
T18	2326	0	0	0
T19	24156	0	0	0
T20	1084	0	0	0
T21	1484	0	0	0
T22	765	1	0	0
T23	950	0	0	0
T24	1149	0	0	0
T25	1458	0	0	0
T38	0	4	0	0
T39	0	1	0	0
T42	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T157	0	3	0	0
T190	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214234324	5023	0	0
T1	379369	71	0	0
T2	0	1	0	0
T6	44325	1	0	0
T18	2326	1	0	0
T19	24156	51	0	0
T20	1084	0	0	0
T21	1484	1	0	0
T22	765	2	0	0
T23	950	1	0	0
T24	1149	0	0	0
T25	0	1	0	0
T26	1947	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T22
0	1	Covered	T1,T123,T157
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T22
1	0	Covered	T38,T39,T40
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	430131514	3308	0	0
GateOpen_A	430131514	5012	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430131514	3308	0	0
T1	758653	70	0	0
T6	88757	0	0	0
T12	0	1	0	0
T18	4772	0	0	0
T19	52137	0	0	0
T20	2038	0	0	0
T21	2749	0	0	0
T22	1569	1	0	0
T23	2020	0	0	0
T24	2166	0	0	0
T25	2594	0	0	0
T38	0	4	0	0
T39	0	1	0	0
T42	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T157	0	2	0	0
T190	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430131514	5012	0	0
T1	758653	74	0	0
T2	0	1	0	0
T6	88757	1	0	0
T18	4772	1	0	0
T19	52137	51	0	0
T20	2038	0	0	0
T21	2749	1	0	0
T22	1569	2	0	0
T23	2020	1	0	0
T24	2166	0	0	0
T25	0	1	0	0
T26	3973	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T22
0	1	Covered	T1,T123,T157
1	0	Covered	T7,T8,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T22
1	0	Covered	T38,T40,T41
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	219594032	3287	0	0
GateOpen_A	219594032	4992	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219594032	3287	0	0
T1	382801	70	0	0
T6	64542	0	0	0
T12	0	1	0	0
T18	2386	0	0	0
T19	26070	0	0	0
T20	1019	0	0	0
T21	1374	0	0	0
T22	784	1	0	0
T23	1010	0	0	0
T24	1083	0	0	0
T25	1296	0	0	0
T38	0	8	0	0
T40	0	2	0	0
T42	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T157	0	2	0	0
T190	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219594032	4992	0	0
T1	382801	74	0	0
T2	0	1	0	0
T6	64542	1	0	0
T18	2386	1	0	0
T19	26070	51	0	0
T20	1019	0	0	0
T21	1374	1	0	0
T22	784	2	0	0
T23	1010	1	0	0
T24	1083	0	0	0
T25	0	1	0	0
T26	1987	1	0	0