Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	726529100	66430	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	726529100	66430	0	0
T1	1003610	1021	0	0
T2	0	226	0	0
T3	0	140	0	0
T6	329430	0	0	0
T11	0	184	0	0
T12	0	160	0	0
T13	0	71	0	0
T14	0	1319	0	0
T15	0	39	0	0
T16	0	731	0	0
T17	0	473	0	0
T18	12420	0	0	0
T19	38015	0	0	0
T20	10610	0	0	0
T21	7150	0	0	0
T22	7840	0	0	0
T23	9575	0	0	0
T24	10370	0	0	0
T25	13505	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145305820	9869	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	9869	0	0
T1	200722	162	0	0
T2	0	36	0	0
T3	0	21	0	0
T6	65886	0	0	0
T11	0	25	0	0
T12	0	28	0	0
T13	0	13	0	0
T14	0	173	0	0
T15	0	6	0	0
T16	0	108	0	0
T17	0	77	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T24	2074	0	0	0
T25	2701	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145305820	9621	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	9621	0	0
T1	200722	161	0	0
T2	0	34	0	0
T3	0	21	0	0
T6	65886	0	0	0
T11	0	22	0	0
T12	0	28	0	0
T13	0	13	0	0
T14	0	168	0	0
T15	0	6	0	0
T16	0	94	0	0
T17	0	77	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T24	2074	0	0	0
T25	2701	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145305820	13327	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	13327	0	0
T1	200722	205	0	0
T2	0	46	0	0
T3	0	28	0	0
T6	65886	0	0	0
T11	0	37	0	0
T12	0	32	0	0
T13	0	14	0	0
T14	0	269	0	0
T15	0	8	0	0
T16	0	143	0	0
T17	0	97	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T24	2074	0	0	0
T25	2701	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145305820	13341	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	13341	0	0
T1	200722	208	0	0
T2	0	44	0	0
T3	0	28	0	0
T6	65886	0	0	0
T11	0	37	0	0
T12	0	31	0	0
T13	0	13	0	0
T14	0	269	0	0
T15	0	8	0	0
T16	0	150	0	0
T17	0	97	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T24	2074	0	0	0
T25	2701	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	145305820	20272	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	20272	0	0
T1	200722	285	0	0
T2	0	66	0	0
T3	0	42	0	0
T6	65886	0	0	0
T11	0	63	0	0
T12	0	41	0	0
T13	0	18	0	0
T14	0	440	0	0
T15	0	11	0	0
T16	0	236	0	0
T17	0	125	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T24	2074	0	0	0
T25	2701	0	0	0