Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T1,T19,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	145305820	142651189	0	0
AllClkBypReqTrue_A	145305820	115132	0	0
IoClkBypReqFalse_A	145305820	142574585	0	2415
IoClkBypReqTrue_A	145305820	187006	0	0
LcClkBypAckFalse_A	145305820	142654860	0	0
LcClkBypAckTrue_A	145305820	111461	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	142651189	0	0
T1	200722	200311	0	0
T5	13523	13491	0	0
T6	65886	65788	0	0
T7	3191	3163	0	0
T8	1475	1240	0	0
T18	2484	2349	0	0
T19	7603	6506	0	0
T20	2122	1849	0	0
T21	1430	1352	0	0
T26	2028	1972	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	115132	0	0
T1	200722	1050	0	0
T5	13523	0	0	0
T6	65886	0	0	0
T8	1475	80	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	117	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T24	0	94	0	0
T25	0	361	0	0
T26	2028	0	0	0
T104	0	166	0	0
T116	0	166	0	0
T117	0	202	0	0
T118	0	52	0	0
T119	0	46	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	142574585	0	2415
T1	200722	200208	0	3
T5	13523	13489	0	3
T6	65886	65786	0	3
T7	3191	3161	0	3
T8	1475	1243	0	3
T18	2484	2347	0	3
T19	7603	6404	0	3
T20	2122	1621	0	3
T21	1430	1128	0	3
T26	2028	1970	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	187006	0	0
T1	200722	2072	0	0
T5	13523	0	0	0
T6	65886	0	0	0
T8	1475	75	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	343	0	0
T21	1430	222	0	0
T22	1568	0	0	0
T24	0	335	0	0
T25	0	639	0	0
T26	2028	0	0	0
T104	0	371	0	0
T116	0	533	0	0
T117	0	261	0	0
T118	0	215	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	142654860	0	0
T1	200722	200295	0	0
T5	13523	13491	0	0
T6	65886	65788	0	0
T7	3191	3163	0	0
T8	1475	1289	0	0
T18	2484	2349	0	0
T19	7603	6506	0	0
T20	2122	1831	0	0
T21	1430	1213	0	0
T26	2028	1972	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	111461	0	0
T1	200722	1212	0	0
T5	13523	0	0	0
T6	65886	0	0	0
T8	1475	31	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	135	0	0
T21	1430	139	0	0
T22	1568	0	0	0
T24	0	155	0	0
T25	0	296	0	0
T26	2028	0	0	0
T104	0	203	0	0
T116	0	219	0	0
T117	0	122	0	0
T118	0	165	0	0