Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1829027520	13963	0	0
TransStop_A	1829027520	7093	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1829027520	13963	0	0
T1	3189956	223	0	0
T5	270220	0	0	0
T6	489840	0	0	0
T7	25536	34	0	0
T8	5904	0	0	0
T18	19884	23	0	0
T19	217248	0	0	0
T20	8492	0	0	0
T21	11452	0	0	0
T22	0	4	0	0
T23	0	7	0	0
T26	16552	23	0	0
T42	0	4	0	0
T120	0	21	0	0
T121	0	20	0	0
T122	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1829027520	7093	0	0
T1	3189956	120	0	0
T5	270220	0	0	0
T6	489840	0	0	0
T7	25536	11	0	0
T8	5904	0	0	0
T18	19884	16	0	0
T19	217248	0	0	0
T20	8492	0	0	0
T21	11452	0	0	0
T22	0	4	0	0
T23	0	2	0	0
T26	16552	3	0	0
T42	0	4	0	0
T120	0	4	0	0
T121	0	3	0	0
T122	0	4	0	0
T123	0	13	0	0
T124	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457256880	3521	0	0
TransStop_A	457256880	1775	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	3521	0	0
T1	797489	54	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	8	0	0
T8	1476	0	0	0
T18	4971	6	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T26	4138	7	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	6	0	0
T122	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	1775	0	0
T1	797489	23	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	3	0	0
T8	1476	0	0	0
T18	4971	5	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T26	4138	1	0	0
T42	0	1	0	0
T120	0	1	0	0
T122	0	1	0	0
T123	0	3	0	0
T124	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457256880	3545	0	0
TransStop_A	457256880	1802	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	3545	0	0
T1	797489	60	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	11	0	0
T8	1476	0	0	0
T18	4971	5	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	6	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	3	0	0
T122	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	1802	0	0
T1	797489	36	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	3	0	0
T8	1476	0	0	0
T18	4971	4	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T26	4138	1	0	0
T42	0	1	0	0
T120	0	1	0	0
T122	0	1	0	0
T123	0	4	0	0
T124	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457256880	3418	0	0
TransStop_A	457256880	1752	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	3418	0	0
T1	797489	55	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	6	0	0
T8	1476	0	0	0
T18	4971	7	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T26	4138	6	0	0
T42	0	1	0	0
T120	0	3	0	0
T121	0	7	0	0
T122	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	1752	0	0
T1	797489	28	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	2	0	0
T8	1476	0	0	0
T18	4971	4	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	0	0	0
T42	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	457256880	3479	0	0
TransStop_A	457256880	1764	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	3479	0	0
T1	797489	54	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	9	0	0
T8	1476	0	0	0
T18	4971	5	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	4	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	4	0	0
T122	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256880	1764	0	0
T1	797489	33	0	0
T5	67555	0	0	0
T6	122460	0	0	0
T7	6384	3	0	0
T8	1476	0	0	0
T18	4971	3	0	0
T19	54312	0	0	0
T20	2123	0	0	0
T21	2863	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	1	0	0
T42	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0