Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	145305820	16176030	0	64

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	16176030	0	64
T1	200722	775804	0	0
T2	0	17479	0	1
T3	0	12654	0	1
T6	65886	0	0	0
T11	0	21578	0	1
T12	0	9087	0	1
T13	0	3459	0	1
T14	0	151265	0	0
T15	0	3612	0	1
T16	0	81705	0	0
T17	0	0	0	1
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T24	2074	0	0	0
T25	2701	0	0	0
T27	0	761	0	0
T71	0	0	0	1
T125	0	0	0	1
T126	0	0	0	1