Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	146209148	5093131	0	0
clk_enables_rd_A	146209148	30914	0	0
clk_hints_rd_A	146209148	26600	0	0
extclk_ctrl_rd_A	146209148	34533	0	0
extclk_ctrl_regwen_rd_A	146209148	25086	0	0
jitter_enable_rd_A	146209148	40250	0	0
jitter_regwen_rd_A	146209148	29091	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	5093131	0	0
T1	200722	102504	0	0
T6	65886	0	0	0
T14	0	47506	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T24	2074	0	0	0
T25	2701	0	0	0
T28	0	62103	0	0
T64	0	39480	0	0
T65	0	106961	0	0
T66	0	136561	0	0
T67	0	171773	0	0
T68	0	191897	0	0
T69	0	105683	0	0
T70	0	110034	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	30914	0	0
T12	0	5	0	0
T14	0	1003	0	0
T17	0	2	0	0
T34	863	0	0	0
T39	682	0	0	0
T123	8507	2	0	0
T124	1085	0	0	0
T149	0	4	0	0
T150	0	6	0	0
T151	0	3	0	0
T152	0	3	0	0
T153	0	6	0	0
T154	0	3	0	0
T155	2560	0	0	0
T156	1827	0	0	0
T157	1192	0	0	0
T158	2408	0	0	0
T159	2515	0	0	0
T160	2742	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	26600	0	0
T12	0	3	0	0
T14	0	924	0	0
T17	0	12	0	0
T34	863	0	0	0
T39	682	0	0	0
T70	0	3552	0	0
T123	8507	4	0	0
T124	1085	0	0	0
T149	0	7	0	0
T150	0	7	0	0
T151	0	8	0	0
T153	0	7	0	0
T154	0	5	0	0
T155	2560	0	0	0
T156	1827	0	0	0
T157	1192	0	0	0
T158	2408	0	0	0
T159	2515	0	0	0
T160	2742	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	34533	0	0
T2	49693	0	0	0
T3	116046	0	0	0
T4	47554	0	0	0
T12	0	16	0	0
T24	2074	35	0	0
T25	2701	93	0	0
T29	49045	0	0	0
T32	2537	0	0	0
T42	1371	0	0	0
T116	2521	0	0	0
T117	1725	0	0	0
T118	0	14	0	0
T119	0	63	0	0
T123	0	73	0	0
T158	0	60	0	0
T161	0	60	0	0
T162	0	40	0	0
T163	0	74	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	25086	0	0
T14	0	764	0	0
T27	62233	0	0	0
T41	1647	0	0	0
T70	0	3428	0	0
T83	1908	0	0	0
T84	787	0	0	0
T85	2108	0	0	0
T86	1102	0	0	0
T87	1550	0	0	0
T88	1337	0	0	0
T163	20120	51	0	0
T164	0	1375	0	0
T165	0	27	0	0
T166	0	17	0	0
T167	0	58	0	0
T168	0	2186	0	0
T169	0	13	0	0
T170	0	3	0	0
T171	1910	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	40250	0	0
T12	0	111	0	0
T14	0	1349	0	0
T17	0	303	0	0
T34	863	0	0	0
T39	682	0	0	0
T123	8507	240	0	0
T124	1085	0	0	0
T149	0	121	0	0
T150	0	138	0	0
T151	0	122	0	0
T152	0	242	0	0
T153	0	144	0	0
T154	0	34	0	0
T155	2560	0	0	0
T156	1827	0	0	0
T157	1192	0	0	0
T158	2408	0	0	0
T159	2515	0	0	0
T160	2742	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	29091	0	0
T14	157789	906	0	0
T15	11363	0	0	0
T16	109894	0	0	0
T70	0	4252	0	0
T114	69947	0	0	0
T164	0	1752	0	0
T168	0	2707	0	0
T172	0	820	0	0
T173	0	2468	0	0
T174	0	2067	0	0
T175	0	2443	0	0
T176	0	2669	0	0
T177	0	2367	0	0
T178	1609	0	0	0
T179	2031	0	0	0
T180	2403	0	0	0
T181	1634	0	0	0
T182	1293	0	0	0
T183	1325	0	0	0