Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T4,T29
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1462091480	1277677	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1462091480	254385	0	0
SrcBusyKnown_A	1462091480	1435747400	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1462091480	1277677	0	0
T1	2007220	12570	0	0
T2	0	1056	0	0
T3	0	1975	0	0
T4	0	2160	0	0
T5	135230	426	0	0
T6	658860	1094	0	0
T11	0	2788	0	0
T18	24840	0	0	0
T19	76030	0	0	0
T20	21220	0	0	0
T21	14300	0	0	0
T22	15680	0	0	0
T23	19150	0	0	0
T26	20280	0	0	0
T29	0	2256	0	0
T30	0	1314	0	0
T31	0	2073	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	5015990	5009058	0	0
T5	458516	457458	0	0
T6	684486	683398	0	0
T7	40306	40000	0	0
T8	10798	9858	0	0
T18	31234	29716	0	0
T19	337500	293758	0	0
T20	13606	12728	0	0
T21	18416	17538	0	0
T26	26030	25442	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1462091480	254385	0	0
T1	2007220	3585	0	0
T2	0	300	0	0
T3	0	400	0	0
T4	0	392	0	0
T5	135230	120	0	0
T6	658860	220	0	0
T11	0	380	0	0
T18	24840	0	0	0
T19	76030	0	0	0
T20	21220	0	0	0
T21	14300	0	0	0
T22	15680	0	0	0
T23	19150	0	0	0
T26	20280	0	0	0
T29	0	448	0	0
T30	0	252	0	0
T31	0	360	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1462091480	1435747400	0	0
T1	2007220	2004170	0	0
T5	135230	134920	0	0
T6	658860	657890	0	0
T7	31910	31640	0	0
T8	14750	13210	0	0
T18	24840	23500	0	0
T19	76030	65570	0	0
T20	21220	19670	0	0
T21	14300	13530	0	0
T26	20280	19730	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	80058	0	0
DstReqKnown_A	432888242	428258948	0	0
SrcAckBusyChk_A	146209148	22483	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	80058	0	0
T1	200722	929	0	0
T2	0	79	0	0
T3	0	138	0	0
T4	0	102	0	0
T5	13523	34	0	0
T6	65886	76	0	0
T11	0	179	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	110	0	0
T30	0	61	0	0
T31	0	147	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432888242	428258948	0	0
T1	758653	757481	0	0
T5	70610	70434	0	0
T6	88756	88567	0	0
T7	6128	6076	0	0
T8	1417	1268	0	0
T18	4772	4514	0	0
T19	52136	44617	0	0
T20	2037	1889	0	0
T21	2748	2599	0	0
T26	3972	3865	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	22483	0	0
T1	200722	356	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	28	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	32	0	0
T30	0	18	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	114201	0	0
DstReqKnown_A	215565852	214387676	0	0
SrcAckBusyChk_A	146209148	22483	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	114201	0	0
T1	200722	1296	0	0
T2	0	108	0	0
T3	0	199	0	0
T4	0	148	0	0
T5	13523	45	0	0
T6	65886	110	0	0
T11	0	279	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	154	0	0
T30	0	86	0	0
T31	0	207	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215565852	214387676	0	0
T1	379369	379045	0	0
T5	35272	35217	0	0
T6	44325	44284	0	0
T7	3052	3038	0	0
T8	1200	1138	0	0
T18	2326	2257	0	0
T19	24156	22311	0	0
T20	1084	1043	0	0
T21	1484	1443	0	0
T26	1946	1932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	22483	0	0
T1	200722	356	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	28	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	32	0	0
T30	0	18	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	182133	0	0
DstReqKnown_A	107782324	107193340	0	0
SrcAckBusyChk_A	146209148	22483	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	182133	0	0
T1	200722	1840	0	0
T2	0	159	0	0
T3	0	317	0	0
T4	0	247	0	0
T5	13523	56	0	0
T6	65886	173	0	0
T11	0	483	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	241	0	0
T30	0	138	0	0
T31	0	339	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107782324	107193340	0	0
T1	189684	189521	0	0
T5	17636	17608	0	0
T6	22162	22141	0	0
T7	1526	1519	0	0
T8	599	568	0	0
T18	1163	1129	0	0
T19	12078	11155	0	0
T20	542	521	0	0
T21	741	720	0	0
T26	973	966	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	22483	0	0
T1	200722	356	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	28	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	32	0	0
T30	0	18	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	77335	0	0
DstReqKnown_A	460128575	455227437	0	0
SrcAckBusyChk_A	146209148	22483	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	77335	0	0
T1	200722	900	0	0
T2	0	77	0	0
T3	0	137	0	0
T4	0	103	0	0
T5	13523	34	0	0
T6	65886	76	0	0
T11	0	176	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	109	0	0
T30	0	60	0	0
T31	0	136	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460128575	455227437	0	0
T1	797489	796268	0	0
T5	67554	67371	0	0
T6	122459	122261	0	0
T7	6383	6329	0	0
T8	1475	1321	0	0
T18	4971	4702	0	0
T19	54311	46481	0	0
T20	2122	1967	0	0
T21	2862	2708	0	0
T26	4138	4026	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	22483	0	0
T1	200722	356	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	28	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	32	0	0
T30	0	18	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	111370	0	0
DstReqKnown_A	220972206	218625957	0	0
SrcAckBusyChk_A	146209148	21946	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	111370	0	0
T1	200722	1283	0	0
T2	0	106	0	0
T3	0	199	0	0
T4	0	87	0	0
T5	13523	44	0	0
T6	65886	110	0	0
T11	0	278	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	92	0	0
T30	0	62	0	0
T31	0	207	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220972206	218625957	0	0
T1	382800	382214	0	0
T5	38186	38099	0	0
T6	64541	64446	0	0
T7	3064	3038	0	0
T8	708	634	0	0
T18	2385	2256	0	0
T19	26069	22315	0	0
T20	1018	944	0	0
T21	1373	1299	0	0
T26	1986	1932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	21946	0	0
T1	200722	356	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	14	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	16	0	0
T30	0	9	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T4,T29
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	100988	0	0
DstReqKnown_A	432888242	428258948	0	0
SrcAckBusyChk_A	146209148	28654	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	100988	0	0
T1	200722	935	0	0
T2	0	80	0	0
T3	0	138	0	0
T4	0	207	0	0
T5	13523	34	0	0
T6	65886	80	0	0
T11	0	180	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	223	0	0
T30	0	126	0	0
T31	0	141	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432888242	428258948	0	0
T1	758653	757481	0	0
T5	70610	70434	0	0
T6	88756	88567	0	0
T7	6128	6076	0	0
T8	1417	1268	0	0
T18	4772	4514	0	0
T19	52136	44617	0	0
T20	2037	1889	0	0
T21	2748	2599	0	0
T26	3972	3865	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	28654	0	0
T1	200722	361	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	56	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	64	0	0
T30	0	36	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T4,T29
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	142832	0	0
DstReqKnown_A	215565852	214387676	0	0
SrcAckBusyChk_A	146209148	28458	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	142832	0	0
T1	200722	1303	0	0
T2	0	109	0	0
T3	0	198	0	0
T4	0	306	0	0
T5	13523	44	0	0
T6	65886	108	0	0
T11	0	274	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	312	0	0
T30	0	180	0	0
T31	0	206	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215565852	214387676	0	0
T1	379369	379045	0	0
T5	35272	35217	0	0
T6	44325	44284	0	0
T7	3052	3038	0	0
T8	1200	1138	0	0
T18	2326	2257	0	0
T19	24156	22311	0	0
T20	1084	1043	0	0
T21	1484	1443	0	0
T26	1946	1932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	28458	0	0
T1	200722	361	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	56	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	64	0	0
T30	0	36	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T4,T29
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	229298	0	0
DstReqKnown_A	107782324	107193340	0	0
SrcAckBusyChk_A	146209148	28620	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	229298	0	0
T1	200722	1872	0	0
T2	0	155	0	0
T3	0	315	0	0
T4	0	491	0	0
T5	13523	57	0	0
T6	65886	177	0	0
T11	0	490	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	505	0	0
T30	0	288	0	0
T31	0	343	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107782324	107193340	0	0
T1	189684	189521	0	0
T5	17636	17608	0	0
T6	22162	22141	0	0
T7	1526	1519	0	0
T8	599	568	0	0
T18	1163	1129	0	0
T19	12078	11155	0	0
T20	542	521	0	0
T21	741	720	0	0
T26	973	966	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	28620	0	0
T1	200722	361	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	56	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	64	0	0
T30	0	36	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T4,T29
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	97147	0	0
DstReqKnown_A	460128575	455227437	0	0
SrcAckBusyChk_A	146209148	28522	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	97147	0	0
T1	200722	909	0	0
T2	0	75	0	0
T3	0	136	0	0
T4	0	203	0	0
T5	13523	34	0	0
T6	65886	74	0	0
T11	0	175	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	223	0	0
T30	0	123	0	0
T31	0	143	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460128575	455227437	0	0
T1	797489	796268	0	0
T5	67554	67371	0	0
T6	122459	122261	0	0
T7	6383	6329	0	0
T8	1475	1321	0	0
T18	4971	4702	0	0
T19	54311	46481	0	0
T20	2122	1967	0	0
T21	2862	2708	0	0
T26	4138	4026	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	28522	0	0
T1	200722	361	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	56	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	64	0	0
T30	0	36	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Covered	T1,T4,T29
1	0	Covered	T5,T1,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T5
0	1	Unreachable
1	0	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T6
1	1	Covered	T5,T1,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T5
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T5
0	1	-	Covered	T5,T1,T6
0	0	1	Covered	T5,T1,T6
0	0	0	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	146209148	142315	0	0
DstReqKnown_A	220972206	218625957	0	0
SrcAckBusyChk_A	146209148	28253	0	0
SrcBusyKnown_A	146209148	143574740	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	142315	0	0
T1	200722	1303	0	0
T2	0	108	0	0
T3	0	198	0	0
T4	0	266	0	0
T5	13523	44	0	0
T6	65886	110	0	0
T11	0	274	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	287	0	0
T30	0	190	0	0
T31	0	204	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220972206	218625957	0	0
T1	382800	382214	0	0
T5	38186	38099	0	0
T6	64541	64446	0	0
T7	3064	3038	0	0
T8	708	634	0	0
T18	2385	2256	0	0
T19	26069	22315	0	0
T20	1018	944	0	0
T21	1373	1299	0	0
T26	1986	1932	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	28253	0	0
T1	200722	361	0	0
T2	0	30	0	0
T3	0	40	0	0
T4	0	42	0	0
T5	13523	12	0	0
T6	65886	22	0	0
T11	0	38	0	0
T18	2484	0	0	0
T19	7603	0	0	0
T20	2122	0	0	0
T21	1430	0	0	0
T22	1568	0	0	0
T23	1915	0	0	0
T26	2028	0	0	0
T29	0	48	0	0
T30	0	27	0	0
T31	0	36	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	146209148	143574740	0	0
T1	200722	200417	0	0
T5	13523	13492	0	0
T6	65886	65789	0	0
T7	3191	3164	0	0
T8	1475	1321	0	0
T18	2484	2350	0	0
T19	7603	6557	0	0
T20	2122	1967	0	0
T21	1430	1353	0	0
T26	2028	1973	0	0