Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	435917460	484	0	0
StatusRise_A	435917460	484	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435917460	484	0	0
T11	570912	0	0	0
T31	379893	0	0	0
T33	2331	0	0	0
T38	3330	17	0	0
T39	0	2	0	0
T40	0	6	0	0
T41	0	11	0	0
T86	0	5	0	0
T91	0	14	0	0
T121	6063	0	0	0
T122	5418	0	0	0
T123	25521	0	0	0
T124	3255	0	0	0
T155	7680	0	0	0
T184	0	8	0	0
T185	0	8	0	0
T186	0	8	0	0
T187	0	13	0	0
T188	0	3	0	0
T189	4296	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435917460	484	0	0
T11	570912	0	0	0
T31	379893	0	0	0
T33	2331	0	0	0
T38	3330	17	0	0
T39	0	2	0	0
T40	0	6	0	0
T41	0	11	0	0
T86	0	5	0	0
T91	0	14	0	0
T121	6063	0	0	0
T122	5418	0	0	0
T123	25521	0	0	0
T124	3255	0	0	0
T155	7680	0	0	0
T184	0	8	0	0
T185	0	8	0	0
T186	0	8	0	0
T187	0	13	0	0
T188	0	3	0	0
T189	4296	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	145305820	153	0	0
StatusRise_A	145305820	153	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	153	0	0
T11	190304	0	0	0
T31	126631	0	0	0
T33	777	0	0	0
T38	1110	5	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	5	0	0
T121	2021	0	0	0
T122	1806	0	0	0
T123	8507	0	0	0
T124	1085	0	0	0
T155	2560	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	1432	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	153	0	0
T11	190304	0	0	0
T31	126631	0	0	0
T33	777	0	0	0
T38	1110	5	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	5	0	0
T121	2021	0	0	0
T122	1806	0	0	0
T123	8507	0	0	0
T124	1085	0	0	0
T155	2560	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	1432	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	145305820	167	0	0
StatusRise_A	145305820	167	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	167	0	0
T11	190304	0	0	0
T31	126631	0	0	0
T33	777	0	0	0
T38	1110	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	2021	0	0	0
T122	1806	0	0	0
T123	8507	0	0	0
T124	1085	0	0	0
T155	2560	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	1432	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	167	0	0
T11	190304	0	0	0
T31	126631	0	0	0
T33	777	0	0	0
T38	1110	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	2021	0	0	0
T122	1806	0	0	0
T123	8507	0	0	0
T124	1085	0	0	0
T155	2560	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	1432	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	145305820	164	0	0
StatusRise_A	145305820	164	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	164	0	0
T11	190304	0	0	0
T31	126631	0	0	0
T33	777	0	0	0
T38	1110	8	0	0
T40	0	2	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	4	0	0
T121	2021	0	0	0
T122	1806	0	0	0
T123	8507	0	0	0
T124	1085	0	0	0
T155	2560	0	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	3	0	0
T189	1432	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145305820	164	0	0
T11	190304	0	0	0
T31	126631	0	0	0
T33	777	0	0	0
T38	1110	8	0	0
T40	0	2	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	4	0	0
T121	2021	0	0	0
T122	1806	0	0	0
T123	8507	0	0	0
T124	1085	0	0	0
T155	2560	0	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	3	0	0
T189	1432	0	0	0