Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	45416	0	0
CgEnOn_A	2147483647	35962	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	45416	0	0
T1	4900462	393	0	0
T5	431920	3	0	0
T6	709620	3	0	0
T7	39302	11	0	0
T8	9824	3	0	0
T11	1038768	0	0	0
T18	30530	9	0	0
T19	331683	153	0	0
T20	13169	3	0	0
T21	17794	3	0	0
T22	0	1	0	0
T26	25429	10	0	0
T31	863600	0	0	0
T33	16268	0	0	0
T38	19671	25	0	0
T39	0	5	0	0
T40	0	15	0	0
T41	0	25	0	0
T66	0	5	0	0
T86	0	5	0	0
T91	0	25	0	0
T121	12559	0	0	0
T122	8633	0	0	0
T123	43245	0	0	0
T124	20030	0	0	0
T155	12205	0	0	0
T184	0	15	0	0
T185	0	20	0	0
T186	0	15	0	0
T189	26874	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	35962	0	0
T1	2125195	375	0	0
T6	277702	0	0	0
T7	6383	8	0	0
T11	483512	0	0	0
T12	0	3	0	0
T18	13232	0	0	0
T19	142681	0	0	0
T20	5785	0	0	0
T21	7835	0	0	0
T22	2715	4	0	0
T23	3445	0	0	0
T24	3886	0	0	0
T25	4776	0	0	0
T26	0	7	0	0
T31	393675	0	0	0
T33	7502	0	0	0
T38	9519	37	0	0
T39	0	8	0	0
T40	0	18	0	0
T41	0	25	0	0
T42	0	4	0	0
T66	0	4	0	0
T86	0	5	0	0
T91	0	25	0	0
T121	5784	0	0	0
T122	3965	2	0	0
T123	20310	6	0	0
T124	9262	0	0	0
T155	5591	0	0	0
T157	0	10	0	0
T184	0	15	0	0
T185	0	20	0	0
T186	0	15	0	0
T187	0	4	0	0
T189	12661	0	0	0
T190	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	214233917	172	0	0
CgEnOn_A	214233917	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214233917	172	0	0
T11	107433	0	0	0
T31	87459	0	0	0
T33	1643	0	0	0
T38	2085	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	1265	0	0	0
T122	863	0	0	0
T123	4575	0	0	0
T124	2037	0	0	0
T155	1213	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	2864	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214233917	172	0	0
T11	107433	0	0	0
T31	87459	0	0	0
T33	1643	0	0	0
T38	2085	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	1265	0	0	0
T122	863	0	0	0
T123	4575	0	0	0
T124	2037	0	0	0
T155	1213	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	2864	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107116353	172	0	0
CgEnOn_A	107116353	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	172	0	0
T11	53716	0	0	0
T31	43730	0	0	0
T33	822	0	0	0
T38	1043	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	632	0	0	0
T122	432	0	0	0
T123	2286	0	0	0
T124	1019	0	0	0
T155	606	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	1432	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	172	0	0
T11	53716	0	0	0
T31	43730	0	0	0
T33	822	0	0	0
T38	1043	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	632	0	0	0
T122	432	0	0	0
T123	2286	0	0	0
T124	1019	0	0	0
T155	606	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	1432	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107116353	172	0	0
CgEnOn_A	107116353	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	172	0	0
T11	53716	0	0	0
T31	43730	0	0	0
T33	822	0	0	0
T38	1043	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	632	0	0	0
T122	432	0	0	0
T123	2286	0	0	0
T124	1019	0	0	0
T155	606	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	1432	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	172	0	0
T11	53716	0	0	0
T31	43730	0	0	0
T33	822	0	0	0
T38	1043	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	632	0	0	0
T122	432	0	0	0
T123	2286	0	0	0
T124	1019	0	0	0
T155	606	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	1432	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107116353	172	0	0
CgEnOn_A	107116353	172	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	172	0	0
T11	53716	0	0	0
T31	43730	0	0	0
T33	822	0	0	0
T38	1043	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	632	0	0	0
T122	432	0	0	0
T123	2286	0	0	0
T124	1019	0	0	0
T155	606	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	1432	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	172	0	0
T11	53716	0	0	0
T31	43730	0	0	0
T33	822	0	0	0
T38	1043	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	632	0	0	0
T122	432	0	0	0
T123	2286	0	0	0
T124	1019	0	0	0
T155	606	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	1432	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	430131090	172	0	0
CgEnOn_A	430131090	169	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430131090	172	0	0
T11	214931	0	0	0
T31	175026	0	0	0
T33	3393	0	0	0
T38	4305	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T66	0	1	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	2623	0	0	0
T122	1806	0	0	0
T123	8877	0	0	0
T124	4168	0	0	0
T155	2560	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T189	5501	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430131090	169	0	0
T11	214931	0	0	0
T31	175026	0	0	0
T33	3393	0	0	0
T38	4305	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T86	0	1	0	0
T91	0	5	0	0
T121	2623	0	0	0
T122	1806	0	0	0
T123	8877	0	0	0
T124	4168	0	0	0
T155	2560	0	0	0
T184	0	3	0	0
T185	0	4	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	5501	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457256427	153	0	0
CgEnOn_A	457256427	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	153	0	0
T11	223893	0	0	0
T31	188324	0	0	0
T33	3535	0	0	0
T38	3995	5	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	5	0	0
T121	2732	0	0	0
T122	1882	0	0	0
T123	9248	0	0	0
T124	4342	0	0	0
T155	2667	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	5731	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	153	0	0
T11	223893	0	0	0
T31	188324	0	0	0
T33	3535	0	0	0
T38	3995	5	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	5	0	0
T121	2732	0	0	0
T122	1882	0	0	0
T123	9248	0	0	0
T124	4342	0	0	0
T155	2667	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	5731	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457256427	153	0	0
CgEnOn_A	457256427	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	153	0	0
T11	223893	0	0	0
T31	188324	0	0	0
T33	3535	0	0	0
T38	3995	5	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	5	0	0
T121	2732	0	0	0
T122	1882	0	0	0
T123	9248	0	0	0
T124	4342	0	0	0
T155	2667	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	5731	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	153	0	0
T11	223893	0	0	0
T31	188324	0	0	0
T33	3535	0	0	0
T38	3995	5	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	5	0	0
T121	2732	0	0	0
T122	1882	0	0	0
T123	9248	0	0	0
T124	4342	0	0	0
T155	2667	0	0	0
T184	0	2	0	0
T185	0	1	0	0
T186	0	3	0	0
T187	0	4	0	0
T189	5731	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Unreachable
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	219593603	167	0	0
CgEnOn_A	219593603	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219593603	167	0	0
T11	107470	0	0	0
T31	93277	0	0	0
T33	1696	0	0	0
T38	2162	8	0	0
T40	0	2	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	4	0	0
T121	1311	0	0	0
T122	904	0	0	0
T123	4439	0	0	0
T124	2084	0	0	0
T155	1280	0	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	3	0	0
T189	2751	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219593603	164	0	0
T11	107470	0	0	0
T31	93277	0	0	0
T33	1696	0	0	0
T38	2162	8	0	0
T40	0	2	0	0
T41	0	3	0	0
T86	0	2	0	0
T91	0	4	0	0
T121	1311	0	0	0
T122	904	0	0	0
T123	4439	0	0	0
T124	2084	0	0	0
T155	1280	0	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	3	0	0
T189	2751	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	107116353	7307	0	0
CgEnOn_A	107116353	4947	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	7307	0	0
T1	189684	114	0	0
T5	17636	1	0	0
T6	22162	1	0	0
T7	1526	1	0	0
T8	599	1	0	0
T18	1163	1	0	0
T19	12078	51	0	0
T20	542	1	0	0
T21	741	1	0	0
T26	973	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107116353	4947	0	0
T1	189684	108	0	0
T6	22162	0	0	0
T12	0	1	0	0
T18	1163	0	0	0
T19	12078	0	0	0
T20	542	0	0	0
T21	741	0	0	0
T22	382	1	0	0
T23	475	0	0	0
T24	573	0	0	0
T25	726	0	0	0
T38	0	4	0	0
T39	0	1	0	0
T40	0	3	0	0
T42	0	1	0	0
T123	0	2	0	0
T157	0	3	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	214233917	7409	0	0
CgEnOn_A	214233917	5049	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214233917	7409	0	0
T1	379369	111	0	0
T5	35272	1	0	0
T6	44325	1	0	0
T7	3052	1	0	0
T8	1200	1	0	0
T18	2326	1	0	0
T19	24156	51	0	0
T20	1084	1	0	0
T21	1484	1	0	0
T26	1946	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214233917	5049	0	0
T1	379369	105	0	0
T6	44325	0	0	0
T12	0	1	0	0
T18	2326	0	0	0
T19	24156	0	0	0
T20	1084	0	0	0
T21	1484	0	0	0
T22	765	1	0	0
T23	950	0	0	0
T24	1148	0	0	0
T25	1457	0	0	0
T38	0	4	0	0
T39	0	1	0	0
T42	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T157	0	4	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T39,T40
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	430131090	7409	0	0
CgEnOn_A	430131090	5046	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430131090	7409	0	0
T1	758653	114	0	0
T5	70610	1	0	0
T6	88756	1	0	0
T7	6128	1	0	0
T8	1417	1	0	0
T18	4772	1	0	0
T19	52136	51	0	0
T20	2037	1	0	0
T21	2748	1	0	0
T26	3972	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430131090	5046	0	0
T1	758653	108	0	0
T6	88756	0	0	0
T12	0	1	0	0
T18	4772	0	0	0
T19	52136	0	0	0
T20	2037	0	0	0
T21	2748	0	0	0
T22	1568	1	0	0
T23	2020	0	0	0
T24	2165	0	0	0
T25	2593	0	0	0
T38	0	4	0	0
T39	0	1	0	0
T42	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T157	0	3	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T38,T40,T41
1	0	Covered	T7,T8,T5
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	219593603	7383	0	0
CgEnOn_A	219593603	5018	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219593603	7383	0	0
T1	382800	114	0	0
T5	38186	1	0	0
T6	64541	1	0	0
T7	3064	1	0	0
T8	708	1	0	0
T18	2385	1	0	0
T19	26069	51	0	0
T20	1018	1	0	0
T21	1373	1	0	0
T26	1986	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219593603	5018	0	0
T1	382800	108	0	0
T6	64541	0	0	0
T12	0	1	0	0
T18	2385	0	0	0
T19	26069	0	0	0
T20	1018	0	0	0
T21	1373	0	0	0
T22	784	1	0	0
T23	1010	0	0	0
T24	1082	0	0	0
T25	1296	0	0	0
T38	0	8	0	0
T40	0	2	0	0
T42	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T157	0	3	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Covered	T7,T26,T1
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457256427	3674	0	0
CgEnOn_A	457256427	3674	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3674	0	0
T1	797489	54	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	8	0	0
T8	1475	0	0	0
T18	4971	6	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T26	4138	7	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3674	0	0
T1	797489	54	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	8	0	0
T8	1475	0	0	0
T18	4971	6	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	3	0	0
T26	4138	7	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Covered	T7,T26,T1
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457256427	3698	0	0
CgEnOn_A	457256427	3698	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3698	0	0
T1	797489	60	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	11	0	0
T8	1475	0	0	0
T18	4971	5	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	6	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3698	0	0
T1	797489	60	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	11	0	0
T8	1475	0	0	0
T18	4971	5	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	6	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Covered	T7,T26,T1
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457256427	3571	0	0
CgEnOn_A	457256427	3571	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3571	0	0
T1	797489	55	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	6	0	0
T8	1475	0	0	0
T18	4971	7	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T26	4138	6	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	3	0	0
T121	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3571	0	0
T1	797489	55	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	6	0	0
T8	1475	0	0	0
T18	4971	7	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T26	4138	6	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	3	0	0
T121	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T4
1	0	Covered	T7,T26,T1
1	1	Covered	T7,T8,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	457256427	3632	0	0
CgEnOn_A	457256427	3632	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3632	0	0
T1	797489	54	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	9	0	0
T8	1475	0	0	0
T18	4971	5	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	4	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457256427	3632	0	0
T1	797489	54	0	0
T5	67554	0	0	0
T6	122459	0	0	0
T7	6383	9	0	0
T8	1475	0	0	0
T18	4971	5	0	0
T19	54311	0	0	0
T20	2122	0	0	0
T21	2862	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T26	4138	4	0	0
T38	0	5	0	0
T42	0	1	0	0
T120	0	6	0	0
T121	0	4	0	0