Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	621768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3549566

1

T1

854

T2

119962

T4

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1027114	1			T1	281		T2	32538		T4	42
values[0x0]	1446343	1			T1	739		T2	47895		T4	18
values[0x1]	1697877	1			T1	796		T2	56882		T4	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	345158	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3826176

1

T1

1160

T2

128701

T4

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16164	1			T1	20		T2	560		T3	195
valid_sources[0x01]	16501	1			T1	1		T2	504		T3	211
valid_sources[0x02]	15875	1			T1	2		T2	500		T3	212
valid_sources[0x03]	18472	1			T1	18		T2	519		T3	189
valid_sources[0x04]	16037	1			T1	3		T2	529		T3	235
valid_sources[0x05]	15964	1			T1	2		T2	515		T3	197
valid_sources[0x06]	16080	1			T1	2		T2	539		T3	204
valid_sources[0x07]	15676	1			T1	6		T2	573		T3	206
valid_sources[0x08]	15229	1			T1	8		T2	569		T3	187
valid_sources[0x09]	16302	1			T2	505		T3	193		T15	3
valid_sources[0x0a]	17061	1			T1	18		T2	608		T3	230
valid_sources[0x0b]	15990	1			T1	21		T2	518		T3	201
valid_sources[0x0c]	15854	1			T1	3		T2	543		T3	227
valid_sources[0x0d]	17112	1			T1	3		T2	450		T3	182
valid_sources[0x0e]	14998	1			T1	9		T2	554		T3	248
valid_sources[0x0f]	18807	1			T2	548		T3	211		T18	3
valid_sources[0x10]	16288	1			T2	533		T3	198		T17	1
valid_sources[0x11]	17122	1			T1	12		T2	605		T3	199
valid_sources[0x12]	16274	1			T1	3		T2	537		T3	202
valid_sources[0x13]	15640	1			T2	532		T3	206		T96	1
valid_sources[0x14]	15437	1			T1	2		T2	615		T3	182
valid_sources[0x15]	17223	1			T1	2		T2	523		T3	206
valid_sources[0x16]	15109	1			T1	16		T2	542		T3	211
valid_sources[0x17]	17499	1			T1	11		T2	554		T3	243
valid_sources[0x18]	16198	1			T1	5		T2	582		T3	193
valid_sources[0x19]	15654	1			T2	519		T3	221		T15	4
valid_sources[0x1a]	15813	1			T1	23		T2	548		T3	208
valid_sources[0x1b]	14594	1			T2	482		T3	204		T96	1
valid_sources[0x1c]	16629	1			T1	5		T2	489		T3	222
valid_sources[0x1d]	15964	1			T1	9		T2	517		T3	194
valid_sources[0x1e]	17565	1			T1	4		T2	512		T3	188
valid_sources[0x1f]	15978	1			T1	8		T2	516		T3	188
valid_sources[0x20]	15789	1			T1	9		T2	509		T3	215
valid_sources[0x21]	16371	1			T1	4		T2	488		T3	199
valid_sources[0x22]	16333	1			T1	4		T2	587		T3	197
valid_sources[0x23]	17479	1			T1	2		T2	530		T3	194
valid_sources[0x24]	15437	1			T1	1		T2	584		T3	211
valid_sources[0x25]	16256	1			T1	5		T2	552		T3	206
valid_sources[0x26]	16612	1			T1	5		T2	542		T3	171
valid_sources[0x27]	16000	1			T1	6		T2	544		T3	203
valid_sources[0x28]	17298	1			T1	2		T2	580		T3	196
valid_sources[0x29]	15883	1			T2	518		T3	200		T15	5
valid_sources[0x2a]	17285	1			T1	1		T2	543		T3	148
valid_sources[0x2b]	15981	1			T2	542		T3	181		T15	3
valid_sources[0x2c]	16690	1			T1	3		T2	527		T3	183
valid_sources[0x2d]	17051	1			T1	33		T2	536		T3	241
valid_sources[0x2e]	16609	1			T1	2		T2	536		T3	208
valid_sources[0x2f]	15885	1			T1	12		T2	595		T3	236
valid_sources[0x30]	15867	1			T1	5		T2	515		T3	245
valid_sources[0x31]	17197	1			T1	2		T2	568		T3	223
valid_sources[0x32]	15588	1			T1	20		T2	505		T3	202
valid_sources[0x33]	16836	1			T1	34		T2	566		T3	217
valid_sources[0x34]	16373	1			T1	6		T2	506		T3	195
valid_sources[0x35]	15987	1			T1	2		T2	524		T3	192
valid_sources[0x36]	16320	1			T1	7		T2	486		T3	202
valid_sources[0x37]	16001	1			T1	3		T2	531		T3	179
valid_sources[0x38]	15565	1			T1	17		T2	553		T3	254
valid_sources[0x39]	15303	1			T1	9		T2	514		T3	185
valid_sources[0x3a]	15273	1			T2	556		T3	193		T56	2
valid_sources[0x3b]	16129	1			T1	10		T2	542		T3	192
valid_sources[0x3c]	14928	1			T1	9		T2	592		T3	191
valid_sources[0x3d]	17366	1			T1	11		T2	593		T3	198
valid_sources[0x3e]	15829	1			T1	8		T2	602		T3	221
valid_sources[0x3f]	16777	1			T1	3		T2	515		T3	210
valid_sources[0x40]	14510	1			T1	2		T2	513		T3	193
valid_sources[0x41]	17865	1			T1	1		T2	611		T3	208
valid_sources[0x42]	15595	1			T2	483		T3	191		T34	1
valid_sources[0x43]	15085	1			T2	496		T3	192		T17	1
valid_sources[0x44]	15134	1			T1	1		T2	526		T3	211
valid_sources[0x45]	15865	1			T1	1		T2	527		T3	214
valid_sources[0x46]	17375	1			T1	2		T2	543		T3	218
valid_sources[0x47]	16622	1			T1	1		T2	518		T3	201
valid_sources[0x48]	16626	1			T1	1		T2	532		T3	200
valid_sources[0x49]	16101	1			T1	8		T2	529		T3	196
valid_sources[0x4a]	15591	1			T1	3		T2	521		T3	227
valid_sources[0x4b]	14714	1			T1	3		T2	504		T3	177
valid_sources[0x4c]	17435	1			T1	1		T2	498		T3	191
valid_sources[0x4d]	16774	1			T2	508		T3	201		T10	170
valid_sources[0x4e]	15081	1			T1	1		T2	498		T3	250
valid_sources[0x4f]	15814	1			T1	1		T2	575		T3	180
valid_sources[0x50]	16942	1			T1	6		T2	511		T3	220
valid_sources[0x51]	17928	1			T1	10		T2	524		T3	229
valid_sources[0x52]	14704	1			T1	2		T2	533		T3	192
valid_sources[0x53]	16385	1			T1	2		T2	575		T3	213
valid_sources[0x54]	17151	1			T1	1		T2	564		T3	224
valid_sources[0x55]	16353	1			T1	22		T2	538		T3	172
valid_sources[0x56]	16573	1			T1	2		T2	548		T3	191
valid_sources[0x57]	16938	1			T2	524		T3	200		T56	2
valid_sources[0x58]	16491	1			T1	22		T2	576		T3	212
valid_sources[0x59]	15849	1			T1	1		T2	527		T3	203
valid_sources[0x5a]	16636	1			T1	8		T2	502		T3	204
valid_sources[0x5b]	16806	1			T1	1		T2	551		T4	81
valid_sources[0x5c]	17816	1			T1	9		T2	566		T3	260
valid_sources[0x5d]	14686	1			T1	6		T2	560		T3	219
valid_sources[0x5e]	14827	1			T2	496		T3	205		T56	2
valid_sources[0x5f]	16393	1			T2	546		T3	194		T18	6
valid_sources[0x60]	15943	1			T1	14		T2	556		T3	164
valid_sources[0x61]	16467	1			T1	13		T2	601		T3	195
valid_sources[0x62]	14767	1			T1	1		T2	507		T3	186
valid_sources[0x63]	17032	1			T1	2		T2	492		T3	204
valid_sources[0x64]	16503	1			T1	1		T2	546		T3	181
valid_sources[0x65]	15569	1			T1	3		T2	558		T3	194
valid_sources[0x66]	17121	1			T2	533		T3	200		T15	1
valid_sources[0x67]	14547	1			T2	477		T3	213		T96	1
valid_sources[0x68]	15196	1			T1	14		T2	592		T3	215
valid_sources[0x69]	15947	1			T1	4		T2	502		T3	171
valid_sources[0x6a]	16362	1			T2	486		T3	202		T20	4
valid_sources[0x6b]	16124	1			T1	8		T2	520		T3	203
valid_sources[0x6c]	15838	1			T1	12		T2	583		T3	218
valid_sources[0x6d]	16479	1			T1	8		T2	532		T3	189
valid_sources[0x6e]	16457	1			T1	4		T2	516		T3	184
valid_sources[0x6f]	17722	1			T1	13		T2	532		T3	192
valid_sources[0x70]	16755	1			T2	515		T3	214		T56	1
valid_sources[0x71]	15910	1			T1	5		T2	525		T3	199
valid_sources[0x72]	15682	1			T2	512		T3	207		T8	17
valid_sources[0x73]	15750	1			T1	32		T2	585		T3	203
valid_sources[0x74]	16623	1			T1	27		T2	623		T3	212
valid_sources[0x75]	17379	1			T2	519		T3	226		T20	1
valid_sources[0x76]	17357	1			T1	2		T2	527		T3	178
valid_sources[0x77]	16690	1			T1	11		T2	547		T3	182
valid_sources[0x78]	18413	1			T2	568		T3	207		T68	1
valid_sources[0x79]	15261	1			T1	9		T2	540		T3	189
valid_sources[0x7a]	15358	1			T1	3		T2	563		T3	195
valid_sources[0x7b]	16522	1			T1	3		T2	548		T3	202
valid_sources[0x7c]	16019	1			T1	30		T2	544		T3	210
valid_sources[0x7d]	15602	1			T1	4		T2	520		T3	187
valid_sources[0x7e]	17008	1			T1	17		T2	531		T3	226
valid_sources[0x7f]	17707	1			T1	2		T2	502		T3	208
valid_sources[0x80]	16169	1			T1	8		T2	569		T3	185

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

897523

1

T1

133

T2

29727

T4

19

values[0x0]

all_enables

biggest_size

1350031

1

T1

458

T2

45689

T4

4

values[0x1]

all_enables

biggest_size

1302012

1

T1

263

T2

44546

T4

2