Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

Group : clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
TransAes	100.00	1	100	1	64	64
TransHmac	100.00	1	100	1	64	64
TransKmac	100.00	1	100	1	64	64
TransOtbn	100.00	1	100	1	64	64

---

Group Instance : TransAes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransAes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransAes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransAes

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransHmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransHmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransHmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransHmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransKmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransKmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransKmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransKmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

---

Group Instance : TransOtbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance TransOtbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	0	10	100.00

Variables for Group Instance TransOtbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransOtbn

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	0	10	100.00	100	1	1	0

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1309517

1

T1

2732

T2

18330

T4

434

auto[1]

343605103

1

T1

825710

T2

112605

T4

3979

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

309042163

1

T1

820630

T2

998140

T4

4413

auto[1]

35872457

1

T1

7812

T2

129747

T3

55606

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9294

1

T1

14

T2

22

T4

2

auto[1]

344905326

1

T1

828428

T2

112788

T4

4411

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200084251

1

T1

810055

T2

508138

T4

4413

auto[1]

144830369

1

T1

18387

T2

619748

T3

199938

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2638

1

T2

2

T34

100

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T2

2

T10

2

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

429597

1

T1

664

T2

6237

T4

432

auto[0]

auto[1]

auto[0]

auto[1]

413741

1

T1

103

T2

1146

T3

3013

auto[0]

auto[1]

auto[1]

auto[0]

381192

1

T1

1463

T2

9219

T3

13914

auto[0]

auto[1]

auto[1]

auto[1]

78001

1

T1

488

T2

1706

T3

3019

auto[1]

auto[1]

auto[0]

auto[0]

173355914

1

T1

805878

T2

444409

T4

3979

auto[1]

auto[1]

auto[0]

auto[1]

25877323

1

T1

3410

T2

629894

T3

31475

auto[1]

auto[1]

auto[1]

auto[0]

134870036

1

T1

12611

T2

552183

T3

196434

auto[1]

auto[1]

auto[1]

auto[1]

9499522

1

T1

3811

T2

664721

T3

18099

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1250082

1

T1

3256

T2

16372

T4

326

auto[1]

343664538

1

T1

825186

T2

112625

T4

4087

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

316820091

1

T1

823409

T2

106239

T4

4413

auto[1]

28094529

1

T1

5033

T2

654941

T3

71402

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9294

1

T1

14

T2

22

T4

2

auto[1]

344905326

1

T1

828428

T2

112788

T4

4411

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200084251

1

T1

810055

T2

508138

T4

4413

auto[1]

144830369

1

T1

18387

T2

619748

T3

199938

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2618

1

T2

2

T34

100

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T10

2

T14

2

T158

2

auto[0]

auto[1]

auto[0]

auto[0]

381787

1

T1

1037

T2

5599

T4

324

auto[0]

auto[1]

auto[0]

auto[1]

450856

1

T1

242

T2

1186

T3

2297

auto[0]

auto[1]

auto[1]

auto[0]

339294

1

T1

1584

T2

8556

T3

14557

auto[0]

auto[1]

auto[1]

auto[1]

71159

1

T1

379

T2

1009

T3

2701

auto[1]

auto[1]

auto[0]

auto[0]

181104092

1

T1

805926

T2

443731

T4

4087

auto[1]

auto[1]

auto[0]

auto[1]

18139840

1

T1

2850

T2

637274

T3

28708

auto[1]

auto[1]

auto[1]

auto[0]

134989449

1

T1

14848

T2

617244

T3

194442

auto[1]

auto[1]

auto[1]

auto[1]

9428849

1

T1

1562

T2

15470

T3

37696

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139534

1

T1

3573

T2

15290

T4

218

auto[1]

343775086

1

T1

824869

T2

112635

T4

4195

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

307407208

1

T1

820540

T2

997569

T4

4413

auto[1]

37507412

1

T1

7902

T2

130317

T3

43844

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9294

1

T1

14

T2

22

T4

2

auto[1]

344905326

1

T1

828428

T2

112788

T4

4411

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200084251

1

T1

810055

T2

508138

T4

4413

auto[1]

144830369

1

T1

18387

T2

619748

T3

199938

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2630

1

T2

2

T34

100

T24

4

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T2

2

T10

2

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

336972

1

T1

1114

T2

6286

T4

216

auto[0]

auto[1]

auto[0]

auto[1]

407667

1

T1

103

T2

1126

T3

3521

auto[0]

auto[1]

auto[1]

auto[0]

314940

1

T1

1752

T2

6415

T3

13118

auto[0]

auto[1]

auto[1]

auto[1]

72969

1

T1

590

T2

1441

T3

2990

auto[1]

auto[1]

auto[0]

auto[0]

173100697

1

T1

806352

T2

443776

T4

4195

auto[1]

auto[1]

auto[0]

auto[1]

26231239

1

T1

2486

T2

636195

T3

28919

auto[1]

auto[1]

auto[1]

auto[0]

133649131

1

T1

11308

T2

552520

T3

197485

auto[1]

auto[1]

auto[1]

auto[1]

10791711

1

T1

4723

T2

664413

T3

8414

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088108

1

T1

4346

T2

14530

T4

110

auto[1]

343826512

1

T1

824096

T2

112643

T4

4303

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

313073521

1

T1

822774

T2

835782

T4

4413

auto[1]

31841099

1

T1

5668

T2

292104

T3

59645

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9294

1

T1

14

T2

22

T4

2

auto[1]

344905326

1

T1

828428

T2

112788

T4

4411

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200084251

1

T1

810055

T2

508138

T4

4413

auto[1]

144830369

1

T1

18387

T2

619748

T3

199938

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	0	10	100.00
Automatically Generated Cross Bins	10	0	10	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

2630

1

T2

4

T34

100

T10

2

auto[0]

auto[0]

auto[1]

auto[1]

32

1

T2

4

T10

4

T126

2

auto[0]

auto[1]

auto[0]

auto[0]

290589

1

T1

1345

T2

4947

T4

108

auto[0]

auto[1]

auto[0]

auto[1]

417042

1

T1

437

T2

1393

T3

4085

auto[0]

auto[1]

auto[1]

auto[0]

296639

1

T1

1964

T2

6231

T3

11165

auto[0]

auto[1]

auto[1]

auto[1]

76852

1

T1

586

T2

1937

T3

3943

auto[1]

auto[1]

auto[0]

auto[0]

176151474

1

T1

804780

T2

329084

T4

4303

auto[1]

auto[1]

auto[0]

auto[1]

23217470

1

T1

3493

T2

178418

T3

34841

auto[1]

auto[1]

auto[1]

auto[0]

136329273

1

T1

14671

T2

505578

T3

196749

auto[1]

auto[1]

auto[1]

auto[1]

8125987

1

T1

1152

T2

113352

T3

16776

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded