Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	730806410	15359	0	0
GateOpen_A	730806410	22053	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730806410	15359	0	0
T2	1442516	253	0	0
T3	2030028	196	0	0
T4	9900	4	0	0
T10	0	202	0	0
T11	0	87	0	0
T15	43595	0	0	0
T16	5465	0	0	0
T17	18515	0	0	0
T18	3849	0	0	0
T19	3874	0	0	0
T20	10059	0	0	0
T21	0	12	0	0
T31	0	5	0	0
T41	0	39	0	0
T55	7617	0	0	0
T96	0	4	0	0
T97	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	730806410	22053	0	0
T2	1442516	277	0	0
T3	2030028	208	0	0
T4	9900	8	0	0
T8	0	4	0	0
T15	43595	24	0	0
T16	5465	4	0	0
T17	18515	0	0	0
T18	3849	4	0	0
T19	3874	4	0	0
T20	10059	0	0	0
T55	7617	4	0	0
T96	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	80347732	3614	0	0
GateOpen_A	80347732	5287	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347732	3614	0	0
T2	264073	59	0	0
T3	224208	49	0	0
T4	1080	1	0	0
T10	0	50	0	0
T11	0	19	0	0
T15	2822	0	0	0
T16	590	0	0	0
T17	2208	0	0	0
T18	429	0	0	0
T19	426	0	0	0
T20	1107	0	0	0
T21	0	3	0	0
T31	0	1	0	0
T41	0	9	0	0
T55	831	0	0	0
T96	0	1	0	0
T97	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80347732	5287	0	0
T2	264073	65	0	0
T3	224208	52	0	0
T4	1080	2	0	0
T8	0	1	0	0
T15	2822	6	0	0
T16	590	1	0	0
T17	2208	0	0	0
T18	429	1	0	0
T19	426	1	0	0
T20	1107	0	0	0
T55	831	1	0	0
T96	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	160696278	3895	0	0
GateOpen_A	160696278	5568	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160696278	3895	0	0
T2	528148	63	0	0
T3	448418	49	0	0
T4	2160	1	0	0
T10	0	52	0	0
T11	0	23	0	0
T15	5644	0	0	0
T16	1179	0	0	0
T17	4421	0	0	0
T18	859	0	0	0
T19	854	0	0	0
T20	2214	0	0	0
T21	0	3	0	0
T31	0	1	0	0
T41	0	9	0	0
T55	1662	0	0	0
T96	0	1	0	0
T97	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160696278	5568	0	0
T2	528148	69	0	0
T3	448418	52	0	0
T4	2160	2	0	0
T8	0	1	0	0
T15	5644	6	0	0
T16	1179	1	0	0
T17	4421	0	0	0
T18	859	1	0	0
T19	854	1	0	0
T20	2214	0	0	0
T55	1662	1	0	0
T96	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	323122812	3906	0	0
GateOpen_A	323122812	5580	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323122812	3906	0	0
T2	105642	67	0	0
T3	896856	49	0	0
T4	4440	1	0	0
T10	0	49	0	0
T11	0	21	0	0
T15	23419	0	0	0
T16	2464	0	0	0
T17	7924	0	0	0
T18	1707	0	0	0
T19	1729	0	0	0
T20	4492	0	0	0
T21	0	3	0	0
T31	0	1	0	0
T41	0	9	0	0
T55	3416	0	0	0
T96	0	1	0	0
T97	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	323122812	5580	0	0
T2	105642	73	0	0
T3	896856	52	0	0
T4	4440	2	0	0
T8	0	1	0	0
T15	23419	6	0	0
T16	2464	1	0	0
T17	7924	0	0	0
T18	1707	1	0	0
T19	1729	1	0	0
T20	4492	0	0	0
T55	3416	1	0	0
T96	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	166639588	3944	0	0
GateOpen_A	166639588	5618	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166639588	3944	0	0
T2	544653	64	0	0
T3	460546	49	0	0
T4	2220	1	0	0
T10	0	51	0	0
T11	0	24	0	0
T15	11710	0	0	0
T16	1232	0	0	0
T17	3962	0	0	0
T18	854	0	0	0
T19	865	0	0	0
T20	2246	0	0	0
T21	0	3	0	0
T31	0	2	0	0
T41	0	12	0	0
T55	1708	0	0	0
T96	0	1	0	0
T97	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166639588	5618	0	0
T2	544653	70	0	0
T3	460546	52	0	0
T4	2220	2	0	0
T8	0	1	0	0
T15	11710	6	0	0
T16	1232	1	0	0
T17	3962	0	0	0
T18	854	1	0	0
T19	865	1	0	0
T20	2246	0	0	0
T55	1708	1	0	0
T96	0	2	0	0