Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	798463955	80204	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	798463955	80204	0	0
T1	1009900	523	0	0
T2	2925530	1613	0	0
T3	629495	1069	0	0
T4	5775	0	0	0
T8	0	94	0	0
T9	0	60	0	0
T10	0	886	0	0
T11	0	292	0	0
T12	0	632	0	0
T13	0	55	0	0
T14	0	2239	0	0
T15	114665	0	0	0
T16	12830	0	0	0
T17	10310	0	0	0
T18	8530	0	0	0
T19	8640	0	0	0
T20	4675	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159692791	11704	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	11704	0	0
T1	201980	84	0	0
T2	585106	235	0	0
T3	125899	191	0	0
T4	1155	0	0	0
T8	0	15	0	0
T9	0	9	0	0
T10	0	142	0	0
T11	0	48	0	0
T12	0	93	0	0
T13	0	9	0	0
T14	0	355	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159692791	11399	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	11399	0	0
T1	201980	82	0	0
T2	585106	231	0	0
T3	125899	191	0	0
T4	1155	0	0	0
T8	0	15	0	0
T9	0	9	0	0
T10	0	138	0	0
T11	0	48	0	0
T12	0	79	0	0
T13	0	9	0	0
T14	0	349	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159692791	16230	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	16230	0	0
T1	201980	106	0	0
T2	585106	325	0	0
T3	125899	210	0	0
T4	1155	0	0	0
T8	0	19	0	0
T9	0	12	0	0
T10	0	180	0	0
T11	0	59	0	0
T12	0	124	0	0
T13	0	11	0	0
T14	0	456	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159692791	16076	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	16076	0	0
T1	201980	106	0	0
T2	585106	321	0	0
T3	125899	210	0	0
T4	1155	0	0	0
T8	0	19	0	0
T9	0	12	0	0
T10	0	180	0	0
T11	0	60	0	0
T12	0	126	0	0
T13	0	11	0	0
T14	0	453	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159692791	24795	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	24795	0	0
T1	201980	145	0	0
T2	585106	501	0	0
T3	125899	267	0	0
T4	1155	0	0	0
T8	0	26	0	0
T9	0	18	0	0
T10	0	246	0	0
T11	0	77	0	0
T12	0	210	0	0
T13	0	15	0	0
T14	0	626	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0