Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T3 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T15 |
28 |
28 |
0 |
0 |
T16 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T20 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
12758929 |
12743180 |
0 |
0 |
T2 |
10755985 |
10744263 |
0 |
0 |
T3 |
13292164 |
13275167 |
0 |
0 |
T4 |
72125 |
69198 |
0 |
0 |
T15 |
607639 |
85797 |
0 |
0 |
T16 |
66945 |
61829 |
0 |
0 |
T17 |
129581 |
127717 |
0 |
0 |
T18 |
45438 |
40390 |
0 |
0 |
T19 |
45992 |
41215 |
0 |
0 |
T20 |
69750 |
67094 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
958156746 |
940723848 |
0 |
14490 |
T1 |
1211880 |
1210116 |
0 |
18 |
T2 |
3510636 |
3506364 |
0 |
18 |
T3 |
755394 |
754290 |
0 |
18 |
T4 |
6930 |
6600 |
0 |
18 |
T15 |
137598 |
12300 |
0 |
18 |
T16 |
15396 |
14112 |
0 |
18 |
T17 |
12372 |
12150 |
0 |
18 |
T18 |
10236 |
9000 |
0 |
18 |
T19 |
10368 |
9210 |
0 |
18 |
T20 |
5610 |
5340 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2031305310 |
2002583066 |
0 |
16905 |
T1 |
4472648 |
4466236 |
0 |
21 |
T2 |
1727562 |
1725448 |
0 |
21 |
T3 |
4972074 |
4964742 |
0 |
21 |
T4 |
25246 |
24073 |
0 |
21 |
T15 |
166869 |
14914 |
0 |
21 |
T16 |
17860 |
16370 |
0 |
21 |
T17 |
45059 |
44275 |
0 |
21 |
T18 |
12230 |
10752 |
0 |
21 |
T19 |
12384 |
11001 |
0 |
21 |
T20 |
25078 |
23921 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2031305310 |
205187 |
0 |
0 |
T1 |
4472648 |
438 |
0 |
0 |
T2 |
1727562 |
3335 |
0 |
0 |
T3 |
4972074 |
2107 |
0 |
0 |
T4 |
25246 |
16 |
0 |
0 |
T10 |
0 |
278 |
0 |
0 |
T15 |
166869 |
24 |
0 |
0 |
T16 |
17860 |
70 |
0 |
0 |
T17 |
45059 |
159 |
0 |
0 |
T18 |
12230 |
91 |
0 |
0 |
T19 |
12384 |
142 |
0 |
0 |
T20 |
25078 |
18 |
0 |
0 |
T68 |
0 |
137 |
0 |
0 |
T69 |
0 |
38 |
0 |
0 |
T70 |
0 |
171 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
7074401 |
7066555 |
0 |
0 |
T2 |
5517787 |
5512427 |
0 |
0 |
T3 |
7564696 |
7556114 |
0 |
0 |
T4 |
39949 |
38486 |
0 |
0 |
T15 |
303172 |
58349 |
0 |
0 |
T16 |
33689 |
31308 |
0 |
0 |
T17 |
72150 |
71253 |
0 |
0 |
T18 |
22972 |
20599 |
0 |
0 |
T19 |
23240 |
20965 |
0 |
0 |
T20 |
39062 |
37794 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
323122392 |
318705608 |
0 |
0 |
T1 |
750308 |
749201 |
0 |
0 |
T2 |
105642 |
105508 |
0 |
0 |
T3 |
896856 |
895509 |
0 |
0 |
T4 |
4440 |
4236 |
0 |
0 |
T15 |
23419 |
2112 |
0 |
0 |
T16 |
2464 |
2261 |
0 |
0 |
T17 |
7923 |
7788 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
4492 |
4288 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
323122392 |
318698474 |
0 |
2415 |
T1 |
750308 |
749180 |
0 |
3 |
T2 |
105642 |
105508 |
0 |
3 |
T3 |
896856 |
895508 |
0 |
3 |
T4 |
4440 |
4233 |
0 |
3 |
T15 |
23419 |
2094 |
0 |
3 |
T16 |
2464 |
2258 |
0 |
3 |
T17 |
7923 |
7785 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
4492 |
4285 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
323122392 |
28241 |
0 |
0 |
T1 |
750308 |
66 |
0 |
0 |
T2 |
105642 |
354 |
0 |
0 |
T3 |
896856 |
165 |
0 |
0 |
T4 |
4440 |
0 |
0 |
0 |
T15 |
23419 |
0 |
0 |
0 |
T16 |
2464 |
0 |
0 |
0 |
T17 |
7923 |
45 |
0 |
0 |
T18 |
1706 |
26 |
0 |
0 |
T19 |
1728 |
59 |
0 |
0 |
T20 |
4492 |
2 |
0 |
0 |
T68 |
0 |
37 |
0 |
0 |
T69 |
0 |
19 |
0 |
0 |
T70 |
0 |
63 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
17417 |
0 |
0 |
T1 |
201980 |
40 |
0 |
0 |
T2 |
585106 |
243 |
0 |
0 |
T3 |
125899 |
123 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T10 |
0 |
278 |
0 |
0 |
T15 |
22933 |
0 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
2 |
0 |
0 |
T18 |
1706 |
18 |
0 |
0 |
T19 |
1728 |
18 |
0 |
0 |
T20 |
935 |
0 |
0 |
0 |
T68 |
0 |
43 |
0 |
0 |
T69 |
0 |
4 |
0 |
0 |
T70 |
0 |
58 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
19981 |
0 |
0 |
T1 |
201980 |
36 |
0 |
0 |
T2 |
585106 |
278 |
0 |
0 |
T3 |
125899 |
115 |
0 |
0 |
T4 |
1155 |
0 |
0 |
0 |
T15 |
22933 |
0 |
0 |
0 |
T16 |
2566 |
0 |
0 |
0 |
T17 |
2062 |
50 |
0 |
0 |
T18 |
1706 |
15 |
0 |
0 |
T19 |
1728 |
22 |
0 |
0 |
T20 |
935 |
2 |
0 |
0 |
T68 |
0 |
57 |
0 |
0 |
T69 |
0 |
15 |
0 |
0 |
T70 |
0 |
50 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
344890403 |
0 |
0 |
T1 |
829595 |
828941 |
0 |
0 |
T2 |
112927 |
112846 |
0 |
0 |
T3 |
955855 |
955085 |
0 |
0 |
T4 |
4624 |
4498 |
0 |
0 |
T15 |
24396 |
11755 |
0 |
0 |
T16 |
2566 |
2455 |
0 |
0 |
T17 |
8253 |
8199 |
0 |
0 |
T18 |
1778 |
1652 |
0 |
0 |
T19 |
1800 |
1660 |
0 |
0 |
T20 |
4679 |
4610 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
344890403 |
0 |
0 |
T1 |
829595 |
828941 |
0 |
0 |
T2 |
112927 |
112846 |
0 |
0 |
T3 |
955855 |
955085 |
0 |
0 |
T4 |
4624 |
4498 |
0 |
0 |
T15 |
24396 |
11755 |
0 |
0 |
T16 |
2566 |
2455 |
0 |
0 |
T17 |
8253 |
8199 |
0 |
0 |
T18 |
1778 |
1652 |
0 |
0 |
T19 |
1800 |
1660 |
0 |
0 |
T20 |
4679 |
4610 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
323122392 |
320910002 |
0 |
0 |
T1 |
750308 |
749680 |
0 |
0 |
T2 |
105642 |
105564 |
0 |
0 |
T3 |
896856 |
896117 |
0 |
0 |
T4 |
4440 |
4319 |
0 |
0 |
T15 |
23419 |
11286 |
0 |
0 |
T16 |
2464 |
2357 |
0 |
0 |
T17 |
7923 |
7870 |
0 |
0 |
T18 |
1706 |
1585 |
0 |
0 |
T19 |
1728 |
1593 |
0 |
0 |
T20 |
4492 |
4426 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
323122392 |
320910002 |
0 |
0 |
T1 |
750308 |
749680 |
0 |
0 |
T2 |
105642 |
105564 |
0 |
0 |
T3 |
896856 |
896117 |
0 |
0 |
T4 |
4440 |
4319 |
0 |
0 |
T15 |
23419 |
11286 |
0 |
0 |
T16 |
2464 |
2357 |
0 |
0 |
T17 |
7923 |
7870 |
0 |
0 |
T18 |
1706 |
1585 |
0 |
0 |
T19 |
1728 |
1593 |
0 |
0 |
T20 |
4492 |
4426 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160695878 |
160695878 |
0 |
0 |
T1 |
375431 |
375431 |
0 |
0 |
T2 |
528148 |
528148 |
0 |
0 |
T3 |
448418 |
448418 |
0 |
0 |
T4 |
2160 |
2160 |
0 |
0 |
T15 |
5644 |
5644 |
0 |
0 |
T16 |
1179 |
1179 |
0 |
0 |
T17 |
4420 |
4420 |
0 |
0 |
T18 |
859 |
859 |
0 |
0 |
T19 |
854 |
854 |
0 |
0 |
T20 |
2213 |
2213 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
160695878 |
160695878 |
0 |
0 |
T1 |
375431 |
375431 |
0 |
0 |
T2 |
528148 |
528148 |
0 |
0 |
T3 |
448418 |
448418 |
0 |
0 |
T4 |
2160 |
2160 |
0 |
0 |
T15 |
5644 |
5644 |
0 |
0 |
T16 |
1179 |
1179 |
0 |
0 |
T17 |
4420 |
4420 |
0 |
0 |
T18 |
859 |
859 |
0 |
0 |
T19 |
854 |
854 |
0 |
0 |
T20 |
2213 |
2213 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80347326 |
80347326 |
0 |
0 |
T1 |
187715 |
187715 |
0 |
0 |
T2 |
264073 |
264073 |
0 |
0 |
T3 |
224208 |
224208 |
0 |
0 |
T4 |
1080 |
1080 |
0 |
0 |
T15 |
2822 |
2822 |
0 |
0 |
T16 |
589 |
589 |
0 |
0 |
T17 |
2208 |
2208 |
0 |
0 |
T18 |
428 |
428 |
0 |
0 |
T19 |
426 |
426 |
0 |
0 |
T20 |
1107 |
1107 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80347326 |
80347326 |
0 |
0 |
T1 |
187715 |
187715 |
0 |
0 |
T2 |
264073 |
264073 |
0 |
0 |
T3 |
224208 |
224208 |
0 |
0 |
T4 |
1080 |
1080 |
0 |
0 |
T15 |
2822 |
2822 |
0 |
0 |
T16 |
589 |
589 |
0 |
0 |
T17 |
2208 |
2208 |
0 |
0 |
T18 |
428 |
428 |
0 |
0 |
T19 |
426 |
426 |
0 |
0 |
T20 |
1107 |
1107 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166639179 |
165524423 |
0 |
0 |
T1 |
401092 |
400778 |
0 |
0 |
T2 |
544653 |
544262 |
0 |
0 |
T3 |
460545 |
460176 |
0 |
0 |
T4 |
2219 |
2159 |
0 |
0 |
T15 |
11709 |
5642 |
0 |
0 |
T16 |
1231 |
1178 |
0 |
0 |
T17 |
3962 |
3936 |
0 |
0 |
T18 |
853 |
793 |
0 |
0 |
T19 |
864 |
796 |
0 |
0 |
T20 |
2245 |
2212 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
166639179 |
165524423 |
0 |
0 |
T1 |
401092 |
400778 |
0 |
0 |
T2 |
544653 |
544262 |
0 |
0 |
T3 |
460545 |
460176 |
0 |
0 |
T4 |
2219 |
2159 |
0 |
0 |
T15 |
11709 |
5642 |
0 |
0 |
T16 |
1231 |
1178 |
0 |
0 |
T17 |
3962 |
3936 |
0 |
0 |
T18 |
853 |
793 |
0 |
0 |
T19 |
864 |
796 |
0 |
0 |
T20 |
2245 |
2212 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156787308 |
0 |
2415 |
T1 |
201980 |
201686 |
0 |
3 |
T2 |
585106 |
584394 |
0 |
3 |
T3 |
125899 |
125715 |
0 |
3 |
T4 |
1155 |
1100 |
0 |
3 |
T15 |
22933 |
2050 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
2062 |
2025 |
0 |
3 |
T18 |
1706 |
1500 |
0 |
3 |
T19 |
1728 |
1535 |
0 |
3 |
T20 |
935 |
890 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
159692791 |
156794562 |
0 |
0 |
T1 |
201980 |
201707 |
0 |
0 |
T2 |
585106 |
584397 |
0 |
0 |
T3 |
125899 |
125717 |
0 |
0 |
T4 |
1155 |
1103 |
0 |
0 |
T15 |
22933 |
2068 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
2062 |
2028 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
935 |
893 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342577494 |
0 |
2415 |
T1 |
829595 |
828421 |
0 |
3 |
T2 |
112927 |
112788 |
0 |
3 |
T3 |
955855 |
954451 |
0 |
3 |
T4 |
4624 |
4410 |
0 |
3 |
T15 |
24396 |
2180 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
8253 |
8110 |
0 |
3 |
T18 |
1778 |
1563 |
0 |
3 |
T19 |
1800 |
1599 |
0 |
3 |
T20 |
4679 |
4464 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
35142 |
0 |
0 |
T1 |
829595 |
69 |
0 |
0 |
T2 |
112927 |
620 |
0 |
0 |
T3 |
955855 |
455 |
0 |
0 |
T4 |
4624 |
4 |
0 |
0 |
T15 |
24396 |
6 |
0 |
0 |
T16 |
2566 |
23 |
0 |
0 |
T17 |
8253 |
13 |
0 |
0 |
T18 |
1778 |
7 |
0 |
0 |
T19 |
1800 |
14 |
0 |
0 |
T20 |
4679 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342577494 |
0 |
2415 |
T1 |
829595 |
828421 |
0 |
3 |
T2 |
112927 |
112788 |
0 |
3 |
T3 |
955855 |
954451 |
0 |
3 |
T4 |
4624 |
4410 |
0 |
3 |
T15 |
24396 |
2180 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
8253 |
8110 |
0 |
3 |
T18 |
1778 |
1563 |
0 |
3 |
T19 |
1800 |
1599 |
0 |
3 |
T20 |
4679 |
4464 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
34693 |
0 |
0 |
T1 |
829595 |
59 |
0 |
0 |
T2 |
112927 |
614 |
0 |
0 |
T3 |
955855 |
382 |
0 |
0 |
T4 |
4624 |
4 |
0 |
0 |
T15 |
24396 |
6 |
0 |
0 |
T16 |
2566 |
23 |
0 |
0 |
T17 |
8253 |
13 |
0 |
0 |
T18 |
1778 |
9 |
0 |
0 |
T19 |
1800 |
9 |
0 |
0 |
T20 |
4679 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342577494 |
0 |
2415 |
T1 |
829595 |
828421 |
0 |
3 |
T2 |
112927 |
112788 |
0 |
3 |
T3 |
955855 |
954451 |
0 |
3 |
T4 |
4624 |
4410 |
0 |
3 |
T15 |
24396 |
2180 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
8253 |
8110 |
0 |
3 |
T18 |
1778 |
1563 |
0 |
3 |
T19 |
1800 |
1599 |
0 |
3 |
T20 |
4679 |
4464 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
34809 |
0 |
0 |
T1 |
829595 |
77 |
0 |
0 |
T2 |
112927 |
596 |
0 |
0 |
T3 |
955855 |
414 |
0 |
0 |
T4 |
4624 |
4 |
0 |
0 |
T15 |
24396 |
6 |
0 |
0 |
T16 |
2566 |
12 |
0 |
0 |
T17 |
8253 |
21 |
0 |
0 |
T18 |
1778 |
5 |
0 |
0 |
T19 |
1800 |
10 |
0 |
0 |
T20 |
4679 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342577494 |
0 |
2415 |
T1 |
829595 |
828421 |
0 |
3 |
T2 |
112927 |
112788 |
0 |
3 |
T3 |
955855 |
954451 |
0 |
3 |
T4 |
4624 |
4410 |
0 |
3 |
T15 |
24396 |
2180 |
0 |
3 |
T16 |
2566 |
2352 |
0 |
3 |
T17 |
8253 |
8110 |
0 |
3 |
T18 |
1778 |
1563 |
0 |
3 |
T19 |
1800 |
1599 |
0 |
3 |
T20 |
4679 |
4464 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
34904 |
0 |
0 |
T1 |
829595 |
91 |
0 |
0 |
T2 |
112927 |
630 |
0 |
0 |
T3 |
955855 |
453 |
0 |
0 |
T4 |
4624 |
4 |
0 |
0 |
T15 |
24396 |
6 |
0 |
0 |
T16 |
2566 |
12 |
0 |
0 |
T17 |
8253 |
15 |
0 |
0 |
T18 |
1778 |
11 |
0 |
0 |
T19 |
1800 |
10 |
0 |
0 |
T20 |
4679 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
347199334 |
342584687 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |