Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	159692791	156658387	0	0
AllClkBypReqTrue_A	159692791	133797	0	0
IoClkBypReqFalse_A	159692791	156577046	0	2415
IoClkBypReqTrue_A	159692791	210382	0	0
LcClkBypAckFalse_A	159692791	156666834	0	0
LcClkBypAckTrue_A	159692791	125350	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	156658387	0	0
T1	201980	201516	0	0
T2	585106	584066	0	0
T3	125899	125658	0	0
T4	1155	1102	0	0
T15	22933	2062	0	0
T16	2566	2354	0	0
T17	2062	1744	0	0
T18	1706	1397	0	0
T19	1728	1480	0	0
T20	935	892	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	133797	0	0
T1	201980	184	0	0
T2	585106	3301	0	0
T3	125899	582	0	0
T4	1155	0	0	0
T10	0	1243	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	283	0	0
T18	1706	105	0	0
T19	1728	57	0	0
T20	935	0	0	0
T68	0	316	0	0
T69	0	29	0	0
T70	0	149	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	156577046	0	2415
T1	201980	201150	0	3
T2	585106	583924	0	3
T3	125899	125602	0	3
T4	1155	1100	0	3
T15	22933	2050	0	3
T16	2566	2352	0	3
T17	2062	1981	0	3
T18	1706	1308	0	3
T19	1728	1369	0	3
T20	935	890	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	210382	0	0
T1	201980	536	0	0
T2	585106	4699	0	0
T3	125899	1126	0	0
T4	1155	0	0	0
T10	0	2521	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	44	0	0
T18	1706	192	0	0
T19	1728	166	0	0
T20	935	0	0	0
T68	0	267	0	0
T69	0	21	0	0
T70	0	387	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	156666834	0	0
T1	201980	201458	0	0
T2	585106	584114	0	0
T3	125899	125643	0	0
T4	1155	1102	0	0
T15	22933	2062	0	0
T16	2566	2354	0	0
T17	2062	1986	0	0
T18	1706	1393	0	0
T19	1728	1503	0	0
T20	935	892	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	125350	0	0
T1	201980	242	0	0
T2	585106	2821	0	0
T3	125899	729	0	0
T4	1155	0	0	0
T10	0	1419	0	0
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	41	0	0
T18	1706	109	0	0
T19	1728	34	0	0
T20	935	0	0	0
T68	0	175	0	0
T69	0	16	0	0
T70	0	217	0	0