Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1388799032	16743	0	0
TransStop_A	1388799032	8548	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388799032	16743	0	0
T1	3318380	55	0	0
T2	451708	378	0	0
T3	3823420	311	0	0
T4	18500	4	0	0
T10	0	163	0	0
T11	0	126	0	0
T15	97584	0	0	0
T16	10268	21	0	0
T17	33016	0	0	0
T18	7116	0	0	0
T19	7204	0	0	0
T20	18716	0	0	0
T21	0	42	0	0
T56	0	43	0	0
T96	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1388799032	8548	0	0
T1	3318380	20	0	0
T2	451708	167	0	0
T3	3823420	145	0	0
T4	18500	4	0	0
T10	0	102	0	0
T11	0	62	0	0
T15	97584	0	0	0
T16	10268	5	0	0
T17	33016	0	0	0
T18	7116	0	0	0
T19	7204	0	0	0
T20	18716	0	0	0
T21	0	27	0	0
T56	0	22	0	0
T96	0	4	0	0
T97	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	347199758	4195	0	0
TransStop_A	347199758	2128	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	4195	0	0
T1	829595	11	0	0
T2	112927	96	0	0
T3	955855	74	0	0
T4	4625	1	0	0
T10	0	32	0	0
T11	0	33	0	0
T15	24396	0	0	0
T16	2567	6	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	13	0	0
T56	0	10	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	2128	0	0
T1	829595	3	0	0
T2	112927	40	0	0
T3	955855	36	0	0
T4	4625	1	0	0
T10	0	22	0	0
T11	0	17	0	0
T15	24396	0	0	0
T16	2567	2	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	7	0	0
T56	0	5	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	347199758	4165	0	0
TransStop_A	347199758	2126	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	4165	0	0
T1	829595	13	0	0
T2	112927	92	0	0
T3	955855	75	0	0
T4	4625	1	0	0
T10	0	39	0	0
T11	0	29	0	0
T15	24396	0	0	0
T16	2567	5	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	8	0	0
T56	0	11	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	2126	0	0
T1	829595	5	0	0
T2	112927	39	0	0
T3	955855	33	0	0
T4	4625	1	0	0
T10	0	24	0	0
T11	0	13	0	0
T15	24396	0	0	0
T16	2567	2	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	7	0	0
T56	0	5	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	347199758	4159	0	0
TransStop_A	347199758	2155	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	4159	0	0
T1	829595	14	0	0
T2	112927	93	0	0
T3	955855	79	0	0
T4	4625	1	0	0
T10	0	46	0	0
T11	0	33	0	0
T15	24396	0	0	0
T16	2567	6	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	9	0	0
T56	0	10	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	2155	0	0
T1	829595	5	0	0
T2	112927	46	0	0
T3	955855	36	0	0
T4	4625	1	0	0
T10	0	27	0	0
T11	0	18	0	0
T15	24396	0	0	0
T16	2567	0	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	6	0	0
T56	0	5	0	0
T96	0	1	0	0
T97	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	347199758	4224	0	0
TransStop_A	347199758	2139	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	4224	0	0
T1	829595	17	0	0
T2	112927	97	0	0
T3	955855	83	0	0
T4	4625	1	0	0
T10	0	46	0	0
T11	0	31	0	0
T15	24396	0	0	0
T16	2567	4	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	12	0	0
T56	0	12	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	347199758	2139	0	0
T1	829595	7	0	0
T2	112927	42	0	0
T3	955855	40	0	0
T4	4625	1	0	0
T10	0	29	0	0
T11	0	14	0	0
T15	24396	0	0	0
T16	2567	1	0	0
T17	8254	0	0	0
T18	1779	0	0	0
T19	1801	0	0	0
T20	4679	0	0	0
T21	0	7	0	0
T56	0	7	0	0
T96	0	1	0	0