Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 401498780 401496365 0 0
selKnown1 969367176 969364761 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 401498780 401496365 0 0
T1 937988 937985 0 0
T2 1320042 1320042 0 0
T3 1120684 1120684 0 0
T4 5400 5397 0 0
T15 14110 14107 0 0
T16 2947 2944 0 0
T17 10563 10560 0 0
T18 2080 2077 0 0
T19 2077 2074 0 0
T20 5533 5530 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 969367176 969364761 0 0
T1 2250924 2250921 0 0
T2 316926 316926 0 0
T3 2690568 2690568 0 0
T4 13320 13317 0 0
T15 70257 70254 0 0
T16 7392 7389 0 0
T17 23769 23766 0 0
T18 5118 5115 0 0
T19 5184 5181 0 0
T20 13476 13473 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 160695878 160695073 0 0
selKnown1 323122392 323121587 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 160695878 160695073 0 0
T1 375431 375430 0 0
T2 528148 528148 0 0
T3 448418 448418 0 0
T4 2160 2159 0 0
T15 5644 5643 0 0
T16 1179 1178 0 0
T17 4420 4419 0 0
T18 859 858 0 0
T19 854 853 0 0
T20 2213 2212 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 323122392 323121587 0 0
T1 750308 750307 0 0
T2 105642 105642 0 0
T3 896856 896856 0 0
T4 4440 4439 0 0
T15 23419 23418 0 0
T16 2464 2463 0 0
T17 7923 7922 0 0
T18 1706 1705 0 0
T19 1728 1727 0 0
T20 4492 4491 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10CoveredT1,T2,T3 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 160455576 160454771 0 0
selKnown1 323122392 323121587 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 160455576 160454771 0 0
T1 374842 374841 0 0
T2 527821 527821 0 0
T3 448058 448058 0 0
T4 2160 2159 0 0
T15 5644 5643 0 0
T16 1179 1178 0 0
T17 3935 3934 0 0
T18 793 792 0 0
T19 797 796 0 0
T20 2213 2212 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 323122392 323121587 0 0
T1 750308 750307 0 0
T2 105642 105642 0 0
T3 896856 896856 0 0
T4 4440 4439 0 0
T15 23419 23418 0 0
T16 2464 2463 0 0
T17 7923 7922 0 0
T18 1706 1705 0 0
T19 1728 1727 0 0
T20 4492 4491 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T4
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T4
11CoveredT1,T2,T4
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 80347326 80346521 0 0
selKnown1 323122392 323121587 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 80347326 80346521 0 0
T1 187715 187714 0 0
T2 264073 264073 0 0
T3 224208 224208 0 0
T4 1080 1079 0 0
T15 2822 2821 0 0
T16 589 588 0 0
T17 2208 2207 0 0
T18 428 427 0 0
T19 426 425 0 0
T20 1107 1106 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 323122392 323121587 0 0
T1 750308 750307 0 0
T2 105642 105642 0 0
T3 896856 896856 0 0
T4 4440 4439 0 0
T15 23419 23418 0 0
T16 2464 2463 0 0
T17 7923 7922 0 0
T18 1706 1705 0 0
T19 1728 1727 0 0
T20 4492 4491 0 0

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