SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 319385582 | 313589124 | 0 | 0 |
gen_flops.OutputDelay_A | 319385582 | 313574616 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T3 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T15 | 2 | 2 | 0 | 0 |
T16 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 319385582 | 313589124 | 0 | 0 |
T1 | 403960 | 403414 | 0 | 0 |
T2 | 1170212 | 1168794 | 0 | 0 |
T3 | 251798 | 251434 | 0 | 0 |
T4 | 2310 | 2206 | 0 | 0 |
T15 | 45866 | 4136 | 0 | 0 |
T16 | 5132 | 4710 | 0 | 0 |
T17 | 4124 | 4056 | 0 | 0 |
T18 | 3412 | 3006 | 0 | 0 |
T19 | 3456 | 3076 | 0 | 0 |
T20 | 1870 | 1786 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 319385582 | 313574616 | 0 | 4830 |
T1 | 403960 | 403372 | 0 | 6 |
T2 | 1170212 | 1168788 | 0 | 6 |
T3 | 251798 | 251430 | 0 | 6 |
T4 | 2310 | 2200 | 0 | 6 |
T15 | 45866 | 4100 | 0 | 6 |
T16 | 5132 | 4704 | 0 | 6 |
T17 | 4124 | 4050 | 0 | 6 |
T18 | 3412 | 3000 | 0 | 6 |
T19 | 3456 | 3070 | 0 | 6 |
T20 | 1870 | 1780 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 159692791 | 156794562 | 0 | 0 |
gen_flops.OutputDelay_A | 159692791 | 156787308 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159692791 | 156794562 | 0 | 0 |
T1 | 201980 | 201707 | 0 | 0 |
T2 | 585106 | 584397 | 0 | 0 |
T3 | 125899 | 125717 | 0 | 0 |
T4 | 1155 | 1103 | 0 | 0 |
T15 | 22933 | 2068 | 0 | 0 |
T16 | 2566 | 2355 | 0 | 0 |
T17 | 2062 | 2028 | 0 | 0 |
T18 | 1706 | 1503 | 0 | 0 |
T19 | 1728 | 1538 | 0 | 0 |
T20 | 935 | 893 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159692791 | 156787308 | 0 | 2415 |
T1 | 201980 | 201686 | 0 | 3 |
T2 | 585106 | 584394 | 0 | 3 |
T3 | 125899 | 125715 | 0 | 3 |
T4 | 1155 | 1100 | 0 | 3 |
T15 | 22933 | 2050 | 0 | 3 |
T16 | 2566 | 2352 | 0 | 3 |
T17 | 2062 | 2025 | 0 | 3 |
T18 | 1706 | 1500 | 0 | 3 |
T19 | 1728 | 1535 | 0 | 3 |
T20 | 935 | 890 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 159692791 | 156794562 | 0 | 0 |
gen_flops.OutputDelay_A | 159692791 | 156787308 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159692791 | 156794562 | 0 | 0 |
T1 | 201980 | 201707 | 0 | 0 |
T2 | 585106 | 584397 | 0 | 0 |
T3 | 125899 | 125717 | 0 | 0 |
T4 | 1155 | 1103 | 0 | 0 |
T15 | 22933 | 2068 | 0 | 0 |
T16 | 2566 | 2355 | 0 | 0 |
T17 | 2062 | 2028 | 0 | 0 |
T18 | 1706 | 1503 | 0 | 0 |
T19 | 1728 | 1538 | 0 | 0 |
T20 | 935 | 893 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 159692791 | 156787308 | 0 | 2415 |
T1 | 201980 | 201686 | 0 | 3 |
T2 | 585106 | 584394 | 0 | 3 |
T3 | 125899 | 125715 | 0 | 3 |
T4 | 1155 | 1100 | 0 | 3 |
T15 | 22933 | 2050 | 0 | 3 |
T16 | 2566 | 2352 | 0 | 3 |
T17 | 2062 | 2025 | 0 | 3 |
T18 | 1706 | 1500 | 0 | 3 |
T19 | 1728 | 1535 | 0 | 3 |
T20 | 935 | 890 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |