Line Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Module :
prim_subreg_shadow
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T45,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T44,T45,T46 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T44,T45,T46 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Module :
prim_subreg_shadow
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10100 |
10100 |
0 |
0 |
T1 |
10 |
10 |
0 |
0 |
T2 |
10 |
10 |
0 |
0 |
T3 |
10 |
10 |
0 |
0 |
T4 |
10 |
10 |
0 |
0 |
T15 |
10 |
10 |
0 |
0 |
T16 |
10 |
10 |
0 |
0 |
T17 |
10 |
10 |
0 |
0 |
T18 |
10 |
10 |
0 |
0 |
T19 |
10 |
10 |
0 |
0 |
T20 |
10 |
10 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2144912130 |
0 |
0 |
T1 |
5088282 |
5081928 |
0 |
0 |
T2 |
3110886 |
3108178 |
0 |
0 |
T3 |
5971764 |
5964006 |
0 |
0 |
T4 |
29046 |
27888 |
0 |
0 |
T15 |
135980 |
13898 |
0 |
0 |
T16 |
16058 |
14884 |
0 |
0 |
T17 |
53532 |
52724 |
0 |
0 |
T18 |
11248 |
10092 |
0 |
0 |
T19 |
11344 |
10294 |
0 |
0 |
T20 |
29472 |
28230 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T45,T47 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T45,T47 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T44,T45,T46 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T44,T45,T46 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
325539763 |
320942220 |
0 |
0 |
T1 |
750308 |
749201 |
0 |
0 |
T2 |
105642 |
105508 |
0 |
0 |
T3 |
896856 |
895509 |
0 |
0 |
T4 |
4440 |
4236 |
0 |
0 |
T15 |
23419 |
2112 |
0 |
0 |
T16 |
2464 |
2261 |
0 |
0 |
T17 |
7923 |
7788 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
4492 |
4288 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T45,T47 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T45,T47 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T44,T45,T46 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T44,T45,T46 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
325539763 |
320942220 |
0 |
0 |
T1 |
750308 |
749201 |
0 |
0 |
T2 |
105642 |
105508 |
0 |
0 |
T3 |
896856 |
895509 |
0 |
0 |
T4 |
4440 |
4236 |
0 |
0 |
T15 |
23419 |
2112 |
0 |
0 |
T16 |
2464 |
2261 |
0 |
0 |
T17 |
7923 |
7788 |
0 |
0 |
T18 |
1706 |
1503 |
0 |
0 |
T19 |
1728 |
1538 |
0 |
0 |
T20 |
4492 |
4288 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T45,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T44,T45,T48 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T44,T45,T48 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
161860189 |
160711471 |
0 |
0 |
T1 |
375431 |
375189 |
0 |
0 |
T2 |
528148 |
527872 |
0 |
0 |
T3 |
448418 |
448114 |
0 |
0 |
T4 |
2160 |
2118 |
0 |
0 |
T15 |
5644 |
1056 |
0 |
0 |
T16 |
1179 |
1131 |
0 |
0 |
T17 |
4420 |
4379 |
0 |
0 |
T18 |
859 |
818 |
0 |
0 |
T19 |
854 |
826 |
0 |
0 |
T20 |
2213 |
2144 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T45,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T45,T48,T49 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T45,T48,T49 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
161860189 |
160711471 |
0 |
0 |
T1 |
375431 |
375189 |
0 |
0 |
T2 |
528148 |
527872 |
0 |
0 |
T3 |
448418 |
448114 |
0 |
0 |
T4 |
2160 |
2118 |
0 |
0 |
T15 |
5644 |
1056 |
0 |
0 |
T16 |
1179 |
1131 |
0 |
0 |
T17 |
4420 |
4379 |
0 |
0 |
T18 |
859 |
818 |
0 |
0 |
T19 |
854 |
826 |
0 |
0 |
T20 |
2213 |
2144 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T45,T46 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T45,T46 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T45,T47,T50 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T45,T47,T50 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80929489 |
80355261 |
0 |
0 |
T1 |
187715 |
187595 |
0 |
0 |
T2 |
264073 |
263935 |
0 |
0 |
T3 |
224208 |
224056 |
0 |
0 |
T4 |
1080 |
1059 |
0 |
0 |
T15 |
2822 |
528 |
0 |
0 |
T16 |
589 |
565 |
0 |
0 |
T17 |
2208 |
2187 |
0 |
0 |
T18 |
428 |
407 |
0 |
0 |
T19 |
426 |
412 |
0 |
0 |
T20 |
1107 |
1072 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T46,T49 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T46,T49 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T45,T49,T47 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T45,T49,T47 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
80929489 |
80355261 |
0 |
0 |
T1 |
187715 |
187595 |
0 |
0 |
T2 |
264073 |
263935 |
0 |
0 |
T3 |
224208 |
224056 |
0 |
0 |
T4 |
1080 |
1059 |
0 |
0 |
T15 |
2822 |
528 |
0 |
0 |
T16 |
589 |
565 |
0 |
0 |
T17 |
2208 |
2187 |
0 |
0 |
T18 |
428 |
407 |
0 |
0 |
T19 |
426 |
412 |
0 |
0 |
T20 |
1107 |
1072 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T46,T49 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T46,T49 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T45,T46,T49 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T45,T46,T49 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349717531 |
344914620 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T46,T47,T50 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T46,T47,T50 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T44,T45,T46 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T44,T45,T46 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
349717531 |
344914620 |
0 |
0 |
T1 |
829595 |
828442 |
0 |
0 |
T2 |
112927 |
112788 |
0 |
0 |
T3 |
955855 |
954452 |
0 |
0 |
T4 |
4624 |
4413 |
0 |
0 |
T15 |
24396 |
2198 |
0 |
0 |
T16 |
2566 |
2355 |
0 |
0 |
T17 |
8253 |
8113 |
0 |
0 |
T18 |
1778 |
1566 |
0 |
0 |
T19 |
1800 |
1602 |
0 |
0 |
T20 |
4679 |
4467 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T46,T47 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T46,T47 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T45,T49,T50 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T45,T49,T50 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167847880 |
165532493 |
0 |
0 |
T1 |
401092 |
400537 |
0 |
0 |
T2 |
544653 |
543986 |
0 |
0 |
T3 |
460545 |
459872 |
0 |
0 |
T4 |
2219 |
2118 |
0 |
0 |
T15 |
11709 |
1055 |
0 |
0 |
T16 |
1231 |
1130 |
0 |
0 |
T17 |
3962 |
3895 |
0 |
0 |
T18 |
853 |
752 |
0 |
0 |
T19 |
864 |
769 |
0 |
0 |
T20 |
2245 |
2144 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
TOTAL | | 16 | 16 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 100 | 6 | 6 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 0 | 0 | |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 0 | 0 | |
CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
CONT_ASSIGN | 161 | 0 | 0 | |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
94 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
|
|
|
MISSING_ELSE |
113 |
1 |
1 |
114 |
|
unreachable |
138 |
1 |
1 |
139 |
|
unreachable |
160 |
1 |
1 |
161 |
|
unreachable |
180 |
1 |
1 |
183 |
1 |
1 |
184 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
189 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Total | Covered | Percent |
Conditions | 26 | 25 | 96.15 |
Logical | 26 | 25 | 96.15 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T44,T49,T47 |
1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T4 |
0 | 1 | Covered | T44,T45,T46 |
1 | 0 | Covered | T2,T3,T15 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T44,T49,T47 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T4 |
1 | 0 | 1 | Unreachable | |
1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | 1 | Covered | T44,T49,T47 |
1 | 1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | 1 | Unreachable | |
1 | 1 | 0 | 1 | Unreachable | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T44,T49,T47 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T4 |
1 | Covered | T44,T45,T46 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
183 |
2 |
2 |
100.00 |
IF |
100 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 183 (((~staged_q) != wr_data)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 100 if ((!rst_ni))
-2-: 102 if ((wr_en && (!err_storage)))
-3-: 104 if ((phase_clear || err_storage))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T4 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T2,T3,T15 |
0 |
0 |
0 |
Covered |
T1,T2,T4 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Assertion Details
CheckSwAccessIsLegal_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1010 |
1010 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T15 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167847880 |
165532493 |
0 |
0 |
T1 |
401092 |
400537 |
0 |
0 |
T2 |
544653 |
543986 |
0 |
0 |
T3 |
460545 |
459872 |
0 |
0 |
T4 |
2219 |
2118 |
0 |
0 |
T15 |
11709 |
1055 |
0 |
0 |
T16 |
1231 |
1130 |
0 |
0 |
T17 |
3962 |
3895 |
0 |
0 |
T18 |
853 |
752 |
0 |
0 |
T19 |
864 |
769 |
0 |
0 |
T20 |
2245 |
2144 |
0 |
0 |