Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	159692791	14438251	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159692791	14438251	0	57
T1	201980	35546	0	1
T2	585106	889406	0	0
T3	125899	465317	0	0
T4	1155	0	0	0
T8	0	6659	0	1
T9	0	6645	0	1
T10	0	59487	0	0
T11	0	19460	0	0
T12	0	70319	0	0
T13	0	3669	0	1
T15	22933	0	0	0
T16	2566	0	0	0
T17	2062	0	0	0
T18	1706	0	0	0
T19	1728	0	0	0
T20	935	0	0	0
T21	0	1452	0	1
T98	0	0	0	1
T99	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1